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tms320vc5503 fixed-point digital signal processor data manual literature number: sprs245j april 2004 ? revised january 2008

revision history 3 april 2004 ? revised january 2008 sprs245j revision history this revision history highlights the technical changes made to sprs245i to generate sprs245j. page(s) no. additions/changes/deletions 18 table 2?3, signal descriptions (continued): ? updated/changed d[15:0] function description from ?... the data bus keepers are disabled at reset, ...? to ?... the data bus keepers are enabled at reset, ...?.
revision history 4 april 2004 ? revised january 2008 sprs245j
contents 5 april 2004 ? revised january 2008 sprs245j contents section page 1 tms320vc5503 features 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 description 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 pin assignments 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 terminal assignments for the ghh package 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 pin assignments for the pge package 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 signal descriptions 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional overview 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 memory 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 on-chip dual-access ram (daram) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 on-chip read-only memory (rom) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 memory maps 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 boot configuration 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 peripherals 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 direct memory access (dma) controller 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 dma channel control register (dma_ccr) 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 i 2 c interface 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 configurable external buses 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 external bus selection register (ebsr) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 parallel port 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 parallel port signal routing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 general-purpose input/output (gpio) ports 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 dedicated general-purpose i/o 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 address bus general-purpose i/o 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 ehpi general-purpose i/o 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 system register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 memory-mapped registers 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 peripheral register description 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 interrupts 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 ifr and ier registers 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 interrupt timing 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 waking up from idle condition 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 idling clock domain when external parallel bus operating in ehpi mode 62 . . . . . . 4 support 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 notices concerning jtag (ieee 1149.1) boundary scan test capability 63 . . . . . . . . . . . . . . . . . 4.1.1 initialization requirements for boundary scan test 63 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 boundary scan description language (bsdl) model 63 . . . . . . . . . . . . . . . . . . . . . . . . 4.2 documentation support 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 device and development-support tool nomenclature 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 tms320vc5503 device nomenclature 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
contents 6 april 2004 ? revised january 2008 sprs245j section page 5 electrical specifications 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 absolute maximum ratings 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 recommended operating conditions 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 recommended operating conditions for cv dd = 1.2 v (108 mhz) 66 . . . . . . . . . . . . . 5.2.2 recommended operating conditions for cv dd = 1.35 v (144 mhz) 67 . . . . . . . . . . . 5.2.3 recommended operating conditions for cv dd = 1.6 v (200 mhz) 68 . . . . . . . . . . . . . 5.3 electrical characteristics 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 electrical characteristics over recommended operating case temperature range for cv dd = 1.2 v (108 mhz) 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 electrical characteristics over recommended operating case temperature range for cv dd = 1.35 v (144 mhz) 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 electrical characteristics over recommended operating case temperature range for cv dd = 1.6 v (200 mhz) 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 esd performance 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 timing parameter symbology 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 clock options 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 internal system oscillator with external crystal 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 layout considerations 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 clock generation in bypass mode (dpll disabled) 75 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.4 clock generation in lock mode (dpll synthesis enabled) 76 . . . . . . . . . . . . . . . . . . . 5.6.5 real-time clock oscillator with external crystal 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 memory interface timings 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 asynchronous memory timings 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 synchronous dram (sdram) timings 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 reset timings 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 power-up reset (on-chip oscillator active) 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 power-up reset (on-chip oscillator inactive) 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 warm reset 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 external interrupt timings 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 wake-up from idle 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 xf timings 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 general-purpose input/output (gpiox) timings 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 tin/tout timings (timer0 only) 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 multichannel buffered serial port (mcbsp) timings 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.1 mcbsp0 timings 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.2 mcbsp1 and mcbsp2 timings 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.3 mcbsp as spi master or slave timings 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.4 mcbsp general-purpose i/o timings 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 enhanced host-port interface (ehpi) timings 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 i 2 c timings 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mechanical data 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 package thermal resistance characteristics 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 packaging information 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
figures 7 april 2004 ? revised january 2008 sprs245j list of figures figure page 2?1 179-terminal ghh ball grid array (bottom view) 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 144-pin pge low-profile quad flatpack (top view) 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 block diagram of the tms320vc5503 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 tms320vc5503 memory map (pge package) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 tms320vc5503 memory map (ghh package) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4 dma_ccr bit locations 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 external bus selection register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 parallel port signal routing 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 parallel port (emif) signal interface 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 i/o direction register (iodir) bit layout 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 i/o data register (iodata) bit layout 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10 address/gpio enable register (agpioen) bit layout 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11 address/gpio direction register (agpiodir) bit layout 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?12 address/gpio data register (agpiodata) bit layout 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13 ehpi gpio enable register (ehpigpioen) bit layout 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?14 ehpi gpio direction register (ehpigpiodir) bit layout 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?15 ehpi gpio data register (ehpigpiodata) bit layout 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16 system register bit locations 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17 ifr0 and ier0 bit locations 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 ifr1 and ier1 bit locations 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 device nomenclature for the tms320vc5503 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 3.3-v test load circuit 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?2 internal system oscillator with external crystal 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?3 bypass mode clock timings 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?4 external multiply-by-n clock timings 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?5 real-time clock oscillator with external crystal 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?6 asynchronous memory read timings 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?7 asynchronous memory write timings 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?8 three sdram read commands 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 three sdram wrt commands 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 sdram actv command 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?11 sdram dcab command 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?12 sdram refr command 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?13 sdram mrs command 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?14 sdram self-refresh command 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
figures 8 april 2004 ? revised january 2008 sprs245j figure page 5?15 power-up reset (on-chip oscillator active) timings 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?16 power-up reset (on-chip oscillator inactive) timings 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?17 reset timings 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?18 external interrupt timings 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?19 wake-up from idle timings 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?20 xf timings 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?21 general-purpose input/output (iox) signal timings 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?22 tin/tout timings when configured as inputs 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?23 tin/tout timings when configured as outputs 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?24 mcbsp receive timings 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?25 mcbsp transmit timings 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?26 mcbsp timings as spi master or slave: clkstp = 10b, clkxp = 0 102 . . . . . . . . . . . . . . . . . . . . . . . 5?27 mcbsp timings as spi master or slave: clkstp = 11b, clkxp = 0 104 . . . . . . . . . . . . . . . . . . . . . . . 5?28 mcbsp timings as spi master or slave: clkstp = 10b, clkxp = 1 106 . . . . . . . . . . . . . . . . . . . . . . . 5?29 mcbsp timings as spi master or slave: clkstp = 11b, clkxp = 1 108 . . . . . . . . . . . . . . . . . . . . . . . 5?30 mcbsp general-purpose i/o timings 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?31 hint timings 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?32 ehpi nonmultiplexed read/write timings 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?33 ehpi multiplexed memory (hpid) read/write timings without autoincrement 112 . . . . . . . . . . . . . . . . 5?34 ehpi multiplexed memory (hpid) read timings with autoincrement 113 . . . . . . . . . . . . . . . . . . . . . . . . 5?35 ehpi multiplexed memory (hpid) write timings with autoincrement 114 . . . . . . . . . . . . . . . . . . . . . . . . 5?36 ehpi multiplexed register read/write timings 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?37 i 2 c receive timings 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?38 i 2 c transmit timings 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tables 9 april 2004 ? revised january 2008 sprs245j list of tables table page 2?1 pin assignments for the ghh package 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 pin assignments for the pge package 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 signal descriptions 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 daram blocks 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 boot configuration summary 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 synchronization control function 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4 external bus selection register bit field description 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 tms320vc5503 parallel port signal routing 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 i/o direction register (iodir) bit functions 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 i/o data register (iodata) bit functions 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 address/gpio enable register (agpioen) bit functions 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 address/gpio direction register (agpiodir) bit functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10 address/gpio data register (agpiodata) bit functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11 ehpi gpio enable register (ehpigpioen) bit functions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?12 ehpi gpio direction register (ehpigpiodir) bit functions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13 ehpi gpio data register (ehpigpiodata) bit functions 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?14 system register bit fields 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?15 cpu memory-mapped registers 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16 idle control, status, and system registers 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17 external memory interface registers 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?18 dma configuration registers 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?19 real-time clock registers 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?20 clock generator 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?21 timers 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?22 multichannel serial port #0 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?23 multichannel serial port #1 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?24 multichannel serial port #2 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?25 gpio 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?26 device revision id 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?27 i 2 c module registers 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?28 watchdog timer registers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?29 external bus selection register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?30 interrupt table 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?31 ifr0 and ier0 register bit fields 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?32 ifr1 and ier1 register bit fields 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 recommended crystal parameters 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?2 clkin timing requirements 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?3 clkout switching characteristics 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?4 multiply-by-n clock option timing requirements 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?5 multiply-by-n clock option switching characteristics 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?6 recommended rtc crystal parameters 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?7 asynchronous memory cycle timing requirements 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?8 asynchronous memory cycle switching characteristics 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tables 10 april 2004 ? revised january 2008 sprs245j table page 5?9 synchronous dram cycle timing requirements 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 synchronous dram cycle switching characteristics 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?11 power-up reset (on-chip oscillator active) timing requirements 89 . . . . . . . . . . . . . . . . . . . . . . . . . 5?12 power-up reset (on-chip oscillator inactive) timing requirements 90 . . . . . . . . . . . . . . . . . . . . . . . . 5?13 power-up reset (on-chip oscillator inactive) switching characteristics 90 . . . . . . . . . . . . . . . . . . . . 5?14 reset timing requirements 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?15 reset switching characteristics 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?16 external interrupt timing requirements 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?17 wake-up from idle switching characteristics 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?18 xf switching characteristics 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?19 gpio pins configured as inputs timing requirements 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?20 gpio pins configured as outputs switching characteristics 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?21 tin/tout pins configured as inputs timing requirements 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?22 tin/tout pins configured as outputs switching characteristics 95 . . . . . . . . . . . . . . . . . . . . . . . . . . 5?23 mcbsp0 timing requirements 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?24 mcbsp0 switching characteristics 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?25 mcbsp1 and mcbsp2 timing requirements 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?26 mcbsp1 and mcbsp2 switching characteristics 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?27 mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0) 101 . . . . . . . . . . 5?28 mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 0) 101 . . . . . . 5?29 mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0) 103 . . . . . . . . . . 5?30 mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 0) 103 . . . . . . . 5?31 mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1) 105 . . . . . . . . . . 5?32 mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 1) 105 . . . . . . 5?33 mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1) 107 . . . . . . . . . . 5?34 mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 1) 107 . . . . . . . 5?35 mcbsp general-purpose i/o timing requirements 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?36 mcbsp general-purpose i/o switching characteristics 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?37 ehpi timing requirements 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?38 ehpi switching characteristics 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?39 i 2 c signals (sda and scl) timing requirements 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?40 i 2 c signals (sda and scl) switching characteristics 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 thermal resistance characteristics (ambient) 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2 thermal resistance characteristics (case) 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
features 11 april 2004 ? revised january 2008 sprs245j 1 tms320vc5503 features high-performance, low-power, fixed-point tms320c55x ? digital signal processor ? 9.26-, 6.95-, 5-ns instruction cycle time ? 108-, 144-, 200-mhz clock rate ? one/two instruction(s) executed per cycle ? dual multipliers [up to 400 million multiply-accumulates per second (mmacs)] ? two arithmetic/logic units (alus) ? three internal data/operand read buses and two internal data/operand write buses 32k x 16-bit on-chip ram, composed of: ? 64k bytes of dual-access ram (daram) 8 blocks of 4k 16-bit 64k bytes of one-wait-state on-chip rom (32k 16-bit) 8m 16-bit maximum addressable external memory space (synchronous dram) 16-bit external parallel bus memory supporting either: ? external memory interface (emif) with gpio capabilities and glueless interface to: ? asynchronous static ram (sram) ? asynchronous eprom ? synchronous dram (sdram) ? 16-bit parallel enhanced host-port interface (ehpi) with gpio capabilities programmable low-power control of six device functional domains on-chip scan-based emulation logic on-chip peripherals ? two 20-bit timers ? watchdog timer ? six-channel direct memory access (dma) controller ? three multichannel buffered serial ports (mcbsps) ? programmable phase-locked loop clock generator ? seven (lqfp) or eight (bga) general- purpose i/o (gpio) pins and a general- purpose output pin (xf) ? inter-integrated circuit (i 2 c) multi-master and slave interface ? real-time clock (rtc) with crystal input, separate clock domain, separate power supply ieee std 1149.1 ? (jtag) boundary scan logic packages: ? 144-terminal low-profile quad flatpack (lqfp) (pge suffix) ? 179-terminal microstar bga ? (ball grid array) (ghh and zhh suffixes) 1.2-v core (108 mhz), 2.7-v ? 3.6-v i/os 1.35-v core (144 mhz), 2.7-v ? 3.6-v i/os 1.6-v core (200 mhz), 2.7-v ? 3.6-v i/os all trademarks are the property of their respective owners. tms320c55x and microstar bga are trademarks of texas instruments. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture.
introduction 12 april 2004 ? revised january 2008 sprs245j 2 introduction this section describes the main features of the tms320vc5503, lists the pin assignments, and describes the function of each pin. this data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. note: this data manual is designed to be used in conjunction with the tms320c55x ? dsp functional overview (literature number spru312), the tms320c55x dsp cpu reference guide (literature number spru371), and the tms320c55x dsp peripherals overview reference guide (literature number spru317). 2.1 description the tms320vc5503 fixed-point digital signal processor (dsp) is based on the tms320c55x dsp generation cpu processor core. the c55x ? dsp architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. the cpu supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and dma activity. these buses provide the ability to perform up to three data reads and two data writes in a single cycle. in parallel, the dma controller can perform up to two data transfers per cycle independent of the cpu activity. the c55x cpu provides two multiply-accumulate (mac) units, each capable of 17-bit x 17-bit multiplication in a single cycle. a central 40-bit arithmetic/logic unit (alu) is supported by an additional 16-bit alu. use of the alus is under instruction set control, providing the ability to optimize parallel activity and power consumption. these resources are managed in the address unit (au) and data unit (du) of the c55x cpu. the c55x dsp generation supports a variable byte width instruction set for improved code density. the instruction unit (iu) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (pu). the program unit decodes the instructions, directs tasks to au and du resources, and manages the fully protected pipeline. predictive branching capability avoids pipeline flushes on execution of conditional instructions. the 64k bytes of on-chip memory on tms320vc5503 is sufficient for many small hand-held appliances, portable personal appliances, gaming devices, and personal medical care appliances. many of these appliances typically require 64k bytes or smaller amount of on-chip memory and need to operate in standby mode for more than 60% to 70% of the time. for applications that require more than 64k bytes of on-chip memory but less than 128k bytes of memory , texas instruments (ti) offers the tms320vc5507 device, which is based on the tms320c55x dsp core. the general-purpose input and output functions provide sufficient pins for status, interrupts, and bit i/o for lcds, keyboards, and media interfaces. the parallel interface operates in two modes, either as a slave to a microcontroller using the hpi port or as a parallel media interface using the asynchronous emif. serial media is supported through three mcbsps. the 5503 peripheral set includes an external memory interface (emif) that provides glueless access to asynchronous memories like eprom and sram, as well as to high-speed, high-density memories such as synchronous dram. additional peripherals include real-time clock, watchdog timer, and i 2 c multi-master and slave interface. three full-duplex multichannel buffered serial ports (mcbsps) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. the enhanced host-port interface (hpi) is a 16-bit parallel interface used to provide host processor access to 32k bytes of internal memory on the 5503. the hpi can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. the dma controller provides data movement for six independent channel contexts without cpu intervention, providing dma throughput of up to two 16-bit words per cycle. two general-purpose timers, up to eight dedicated general-purpose i/o (gpio) pins, and digital phase-locked loop (dpll) clock generation are also included. c55x, expressdsp, code composer studio, dsp/bios, rtdx, and xds510 are trademarks of texas instruments.
introduction 13 april 2004 ? revised january 2008 sprs245j the 5503 is supported by the industry?s award-winning expressdsp ? , code composer studio ? integrated development environment (ide), dsp/bios ? , texas instruments? algorithm standard, and the industry?s largest third-party network. the code composer studio ide features code generation tools including a c compiler and visual linker, simulator, rtdx ? , xds510 ? emulation device drivers, and evaluation modules. the 5503 is also supported by the c55x dsp library which features more than 50 foundational software kernels (fir filters, iir filters, ffts, and various math functions) as well as chip and board support libraries. 2.2 pin assignments figure 2?1 illustrates the ball locations for the 179-pin ball grid array (bga) package and is used in conjunction with table 2?1 to locate signal names and ball grid numbers. dv dd is the power supply for the i/o pins while cv dd is the power supply for the core. v ss is the ground for both the i/o pins and the core. rcv dd and rdv dd are rtc module core and i/o supply, respectively. 2.2.1 terminal assignments for the ghh and zhh packages 14 12 13 10 11 8 9 p m l j h k n 56 34 g e f d c 12 a b 7 figure 2?1. 179-terminal ghh and zhh ball grid array (bottom view)
introduction 14 april 2004 ? revised january 2008 sprs245j table 2?1. pin assignments for the ghh and zhh packages ball # signal name ball # signal name ball # signal name ball # signal name a2 v ss d5 gpio5 h2 dv dd l13 d15 a3 gpio4 d6 dr0 h3 a19 l14 cv dd a4 dv dd d7 clkr1 h4 c4 m1 c10 a5 fsr0 d8 dr1 h5 c5 m2 c13 a6 cv dd d9 dv dd h10 dv dd m3 v ss a7 fsr1 d10 fsx2 h11 a?[0] m4 cv dd a8 dv dd d11 v ss h12 reset m5 v ss a9 clkr2 d12 nc h13 sda m6 a5 a10 dr2 d13 nc h14 scl m7 a1 a11 dx2 d14 nc j1 c6 m8 a15 a12 rtcinx1 e1 gpio1 j2 dv dd m9 d3 a13 rdv dd e2 gpio2 j3 c7 m10 d6 a14 rdv dd e3 dv dd j4 c8 m11 cv dd b1 v ss e4 v ss j5 cv dd m12 dv dd b2 cv dd e5 v ss j10 cv dd m13 v ss b3 gpio3 e6 dv dd j11 cv dd m14 d12 b4 tin/tout0 e7 dx0 j12 trst n1 v ss b5 clkr0 e8 fsx1 j13 tck n2 v ss b6 fsx0 e9 dx1 j14 tms n3 a13 b7 cv dd e10 nc k1 a18 n4 a10 b8 cv dd e11 nc k2 c9 n5 a7 b9 v ss e12 v ss k3 c11 n6 dv dd b10 clkx2 e13 v ss k4 v ss n7 cv dd b11 v ss e14 xf k5 v ss n8 cv dd b12 rtcinx2 f1 x1 k6 a3 n9 v ss b13 rdv dd f2 x2/clkin k7 a2 n10 v ss b14 v ss f3 gpio0 k8 d1 n11 d8 c1 nc f4 v ss k9 a14 n12 d11 c2 v ss f5 clkout k10 dv dd n13 dv dd c3 nc f10 dv dd k11 emu0 n14 v ss c4 gpio6 f11 v ss k12 emu1/off p1 v ss c5 v ss f12 int4 k13 tdo p2 v ss c6 clkx0 f13 dv dd k14 tdi p3 a12 c7 v ss f14 int3 l1 cv dd p4 a9 c8 clkx1 g1 cv dd l2 c14 p5 a17 c9 fsr2 g2 c1 l3 c12 p6 a4 c10 cv dd g3 a20 l4 a11 p7 a16 c11 v ss g4 c2 l5 a8 p8 dv dd c12 rcv dd g5 c0 l6 a6 p9 d2 c13 v ss g10 int2 l7 a0 p10 d5 c14 dv dd g11 cv dd l8 d0 p11 d7 d1 gpio7 g12 v ss l9 d4 p12 d10 d2 dv dd g13 int1 l10 d9 p13 dv dd d3 rsvd2 g14 int0 l11 d13 p14 dv dd d4 rsvd1 h1 c3 l12 d14
introduction 15 april 2004 ? revised january 2008 sprs245j 2.2.2 pin assignments for the pge package the tms320vc5503pge 144-pin low-profile quad flatpack (lqfp) pin assignments are shown in figure 2?2 and is used in conjunction with table 2?2 to locate signal names and pin numbers. dv dd is the power supply for the i/o pins while cv dd is the power supply for the core. v ss is the ground for both the i/o pins and the core. rcv dd and rdv dd are rtc module core and i/o supply, respectively. 72 37 73 36 108 109 144 1 figure 2?2. 144-pin pge low-profile quad flatpack (top view)
introduction 16 april 2004 ? revised january 2008 sprs245j table 2?2. pin assignments for the pge package pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 v ss 37 v ss 73 v ss 109 rdv dd 2 nc 38 a13 74 d12 110 rcv dd 3 rsvd1 39 a12 75 d13 111 rtcinx2 4 rsvd2 40 a11 76 d14 112 rtcinx1 5 dv dd 41 cv dd 77 d15 113 v ss 6 gpio7 42 a10 78 cv dd 114 v ss 7 v ss 43 a9 79 emu0 115 v ss 8 dv dd 44 a8 80 emu1/off 116 dx2 9 gpio2 45 v ss 81 tdo 117 fsx2 10 gpio1 46 a7 82 tdi 118 cv dd 11 v ss 47 a6 83 cv dd 119 clkx2 12 gpio0 48 a5 84 trst 120 dr2 13 x2/clkin 49 dv dd 85 tck 121 fsr2 14 x1 50 a4 86 tms 122 v ss 15 clkout 51 a3 87 cv dd 123 clkr2 16 c0 52 a2 88 dv dd 124 dx1 17 c1 53 cv dd 89 sda 125 fsx1 18 cv dd 54 a1 90 scl 126 dv dd 19 c2 55 a0 91 reset 127 clkx1 20 c3 56 dv dd 92 v ss 128 dr1 21 c4 57 d0 93 int0 129 fsr1 22 c5 58 d1 94 int1 130 clkr1 23 c6 59 d2 95 cv dd 131 dx0 24 dv dd 60 v ss 96 int2 132 cv dd 25 c7 61 d3 97 int3 133 fsx0 26 c8 62 d4 98 dv dd 134 clkx0 27 c9 63 d5 99 int4 135 dr0 28 c11 64 v ss 100 v ss 136 fsr0 29 cv dd 65 d6 101 xf 137 clkr0 30 cv dd 66 d7 102 v ss 138 v ss 31 c14 67 d8 103 v ss 139 dv dd 32 c12 68 cv dd 104 dv dd 140 tin/tout0 33 v ss 69 d9 105 nc 141 gpio6 34 c10 70 d10 106 nc 142 gpio4 35 c13 71 d11 107 dv dd 143 gpio3 36 v ss 72 dv dd 108 v ss 144 v ss
introduction 17 april 2004 ? revised january 2008 sprs245j 2.3 signal descriptions table 2?3 lists each signal, function, and operating mode(s) grouped by function. see section 2.2 for pin locations based on package type. table 2?3. signal descriptions terminal name multiplexed signal name i/o/z ? function bk ? reset condition parallel bus a[13:0] i/o/z a subset of the parallel address bus a13?a0 of the c55x ? dsp core bonded to external pins. these pins serve in one of three functions: hpi address bus (hpi.ha[13:0]), emif address bus (emif.a[13:0]), or general-purpose i/o (gpio.a[13:0]). the initial state of these pins depends on the gpio0 pin. see section 3.5.1 for more information. the address bus has a bus holder feature that eliminates passive component requirement and the power dissipation associated with them. the bus holders keep the address bus at the previous logic level when the bus goes into a high-impedance state. gpio0 = 1: hpi.ha[13:0] i hpi address bus. hpi.ha[13:0] is selected when the parallel port mode bit field of the external bus selection register is 10. this setting enables the hpi in non-multiplexed mode. hpi.ha[13:0] provides dsp internal memory access to host. in non-multiplexed mode, these signals are driven by an external host as address lines. bk gpio0 = 1: output, emif.a[13:0] gpio0 = 0: emif.a[13:0] o/z emif address bus. emif.a[13:0] is selected when the parallel port mode bit field of the external bus selection register is 01. this setting enables the full emif mode and the emif drives the parallel port address bus. the internal a[14] address is exclusive-ored with internal a[0] address and the result is routed to the a[0] pin. input, hpi.ha[13:0] gpio.a[13:0] i/o/z general-purpose i/o address bus. gpio.a[13:0] is selected when the parallel port mode bit field of the external bus selection register is 11. this setting enables the hpi in multiplexed mode with the parallel port gpio register controlling the parallel port address bus. gpio is also selected when the parallel port mode bit field is 00, enabling the data emif mode. a [0] (bga only) emif.a [0] o/z emif address bus a [0]. this pin is not multiplexed with emif.a[14] and is used as the least significant external address pin on the bga package. output ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 18 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name parallel bus (continued) a[15:14] (bga only) i/o/z a subset of the parallel address bus a15?a14 of the c55x ? dsp core bonded to external pins. these pins serve in one of two functions: emif address bus (emif.a[15:14]), or general-purpose i/o (gpio.a[15:14]). the initial state of these pins depends on the gpio0 pin. see section 3.5.1 for more information. the address bus has a bus holder feature that eliminates passive component requirement and the power dissipation associated with them. the bus holders keep the address bus at the previous logic level when the bus goes into a high-impedance state. bk gpio0 = 1: output, emif.a[15:14] emif.a[15:14] o/z emif address bus. emif.a[15:14] is selected when the parallel port mode bit field of the external bus selection register is 01. this setting enables the full emif mode and the emif drives the parallel port address bus. bk gpio0 = 0: input, gpio.a[15:14] gpio.a[15:14] i/o/z general-purpose i/o address bus. gpio.a[15:14] is selected when the parallel port mode bit field of the external bus selection register is 11. this setting enables the hpi in multiplexed mode with the parallel port gpio register controlling the parallel port address bus. gpio is also selected when the parallel port mode bit field is 00, enabling the data emif mode. gpio.a[15:14] a[20:16] (bga only) emif.a[20:16] o/z emif address bus. at reset, these address pins are set as output. note: these pins only function as emif address pins and they are not multiplexed for any other function. output d[15:0] i/o/z a subset of the parallel bidirectional data bus d31?d0 of the c55x ? dsp core. these pins serve in one of two functions: emif data bus (emif.d[15:0]) or hpi data bus (hpi.hd[15:0]). the initial state of these pins depends on the gpio0 pin. see section 3.5.1 for more information. the data bus includes bus keepers to reduce the static power dissipation caused by floating, unused pins. this eliminates the need for external bias resistors on unused pins. when the data bus is not being driven by the cpu, the bus keepers keep the pins at the logic level that was most recently driven. (the data bus keepers are enabled at reset, and can be enabled/disabled under software control.) bk gpio0 = 1: input, emif.d[15:0] gpio0 = 0: input, hpi.hd[15:0] emif.d[15:0] i/o/z emif data bus. emif.d[15:0] is selected when the parallel port mode bit field of the external bus selection register is 00 or 01. hpi.hd[15:0] hpi.hd[15:0] i/o/z hpi data bus. hpi.hd[15:0] is selected when the parallel port mode bit field of the external bus selection register is 10 or 11. ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 19 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name parallel bus (continued) c0 i/o/z emif asynchronous memory read enable or general-purpose io8. this pin serves in one of two functions: emif asynchronous memory read enable (emif.are ) or general-purpose io8 (gpio8). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.are emif.are o/z active-low emif asynchronous memory read enable. emif.are is selected when the parallel port mode bit field of the external bus selection register is 00 or 01. bk emif.are gpio0 = 0: input, gpio8 i/o/z general-purpose io8. gpio8 is selected when the parallel port mode bit field of the external bus selection register is set to 10 or 11. input, gpio8 c1 o/z emif asynchronous memory output enable or hpi interrupt output. this pin serves in one of two functions: emif asynchronous memory output enable (emif .aoe ) or hpi interrupt output (hpi.hint ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.aoe emif.aoe o/z active-low asynchronous memory output enable. emif.aoe is selected when the parallel port mode bit field of the external bus selection register is 00 or 01. emif.aoe gpio0 = 0: output, hpi.hint o/z active-low hpi interrupt output. hpi.hint is selected when the parallel port mode bit field of the external bus selection register is 10 or 11. output, hpi.hint c2 i/o/z emif asynchronous memory write enable or hpi read/write. this pin serves in one of two functions: emif asynchronous memory write enable (emif.awe ) or hpi read/write (hpi.hr/w ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.awe emif.awe o/z active-low emif asynchronous memory write enable. emif.awe is selected when the parallel port mode bit field of the external bus selection register is 00 or 01. bk emif.awe gpio0 = 0: input, hpi.hr/w i hpi read/write. hpi.hr/w is selected when the parall el port mode bit field of the external bus selection register is 10 or 11. hpi.hr/w controls the direction of the hpi transfer. input, hpi.hr/w c3 i/o/z emif data ready input or hpi ready output. this pin serves in one of two functions: emif data ready input (emif.ardy) or hpi ready output (hpi.hrdy). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: input, emif.ardy emif.ardy i emif data ready input. used to insert wait states for slow memories. emif.ardy is selected when the parallel port mode bit field of the external bus selection register is 00 or 01. when this pin is used as ardy, an external 2.2 k ? pull?up resistor is recommended. h emif.ardy gpio0 = 0: output, hpi.hrdy hpi.hrdy o hpi ready output. hpi.hrdy is selected when the parallel port mode bit field of the external bus selection register is 10 or 11. hpi.hrdy ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 20 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name parallel bus (continued) c4 i/o/z emif chip select for memory space ce0 or general-purpose io9. this pin serves in one of two functions: emif chip select for memory space ce0 (emif.ce0 ) or general-purpose io9 (gpio9). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.ce0 emif.ce0 o/z active-low emif chip select for memory space ce0. emif .ce0 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.ce0 gpio0 = 0: input, gpio9 i/o/z general-purpose io9. gpio9 is selected when the parallel port mode bit field of the external bus selection register is set to 10 or 11. input, gpio9 c5 i/o/z emif chip select for memory space ce1 or general-purpose io10. this pin serves in one of two functions: emif chip-select for memory space ce1 (emif.ce1 ) or general-purpose io10 (gpio10). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.ce1 emif.ce1 o/z active-low emif chip select for memory space ce1. emif .ce1 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.ce1 gpio0 = 0: input, gpio10 i/o/z general-purpose io10. gpio10 is selected when the parallel port mode bit field of the external bus selection register is set to 10 or 11. input, gpio10 c6 i/o/z emif chip select for memory space ce2 or hpi control input 0. this pin serves in one of two functions: emif chip-select for memory space ce2 (emif.ce2 ) or hpi control input 0 (hpi.hcntl0). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.ce2 o/z active-low emif chip select for memory space ce2. emif .ce2 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk output, emif.ce2 gpio0 = 0: hpi.hcntl0 i hpi control input 0. this pin, in conjunction with hpi.hcntl1, selects a host access to one of the three hpi registers. hpi.hcntl0 is selected when the parallel port mode bit field of the external bus selection register is set to 10 or 11. gpio0 = 0: input, hpi.hcntl0 c7 i/o/z emif chip select for memory space ce3, general-purpose io11, or hpi control input 1. this pin serves in one of three functions: emif chip-select for memory space ce3 (emif.ce3 ), general-purpose io11 (gpio11), or hpi control input 1 (hpi.hcntl1). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.ce3 o/z active-low emif chip select for memory space ce3. emif .ce3 is selected when the parallel port mode bit field is of the external bus selection register set to 00 or 01. bk output, emif.ce3 gpio0 = 0: gpio11 i/o/z general-purpose io11. gpio11 is selected when the parallel port mode bit field is set to 10. gpio0 = 0: input, hpi.hcntl1 hpi.hcntl1 i hpi control input 1. this pin, in conjunction with hpi.hcntl0, selects a host access to one of the three hpi registers. the hpi.hcntl1 mode is selected when the parallel port mode bit field is set to 11. hpi.hcntl1 ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 21 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name parallel bus (continued) c8 i/o/z emif byte enable 0 control or hpi byte identification. this pin serves in one of two functions: emif byte enable 0 control (emif.be0 ) or hpi byte identification (hpi.hbe0 ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.be0 emif.be0 o/z active-low emif byte enable 0 control. emif.be0 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.be0 gpio0 = 0: input, hpi.hbe0 i hpi byte identification. this pin, in conjunction with hpi.hbe1 , identifies the first or second byte of the transfer. hpi.hbe0 is selected when the parallel port mode bit field is set to 10 or 11. input, hpi.hbe0 c9 i/o/z emif byte enable 1 control or hpi byte identification. this pin serves in one of two functions: emif byte enable 1 control (emif.be1 ) or hpi byte identification (hpi.hbe1 ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.be1 emif.be1 o/z active-low emif byte enable 1 control. emif.be1 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.be1 gpio0 = 0: input, hpi.hbe1 i hpi byte identification. this pin, in conjunction with hpi.hbe0 , identifies the first or second byte of the transfer. hpi.hbe1 is selected when the parallel port mode bit field is set to 10 or 11. input, hpi.hbe1 c10 i/o/z emif sdram row strobe, hpi address strobe, or general-purpose io12. this pin serves in one of three functions: emif sdram row strobe (emif.sdras ), hpi address strobe (hpi.has ), or general-purpose io12 (gpio12). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.sdras o/z active-low emif sdram row strobe. emif.sdras is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk output, emif.sdras gpio0 = 0: hpi.has i active-low hpi address strobe. this signal latches the address in the hpia register in the hpi multiplexed mode. hpi.has is selected when the parallel port mode bit field is set to 11. gpio0 = 0: input, hpi.has gpio12 i/o/z general-purpose io12. gpio12 is selected when the parallel port mode bit field is set to 10. ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 22 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name parallel bus (continued) c11 i/o/z emif sdram column strobe or hpi chip select input. this pin serves in one of two functions: emif sdram column strobe (emif .sdcas ) or hpi chip select input (hpi.hcs ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.sdcas emif.sdcas o/z active-low emif sdram column strobe. emif.sdcas is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.sdcas gpio0 = 0: input, hpi.hcs i hpi chip select input. hpi.hcs is the select input for the hpi and must be driven low during accesses. hpi.hcs is selected when the parallel port mode bit field is set to 10 or 11. input, hpi.hcs c12 i/o/z emif sdram write enable or hpi data strobe 1 input. this pin serves in one of two functions: emif sdram write enable (emif.sdwe ) or hpi data strobe 1 (hpi.hds1 ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.sdwe emif.sdwe o/z emif sdram write enable. emif. sdwe is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.sdwe gpio0 = 0: hpi.hds1 i hpi data strobe 1 input. hpi.hds1 is driven by the host read or write strobes to control the transfer. hpi.hds1 is selected when the parallel port mode bit field is set to 10 or 11. gpio0 = 0: input, hpi.hds1 c13 i/o/z sdram a10 address line or general-purpose io13. this pin serves in one of two functions: sdram a10 address line (emif.sda10) or general-purpose io13 (gpio13). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.sda10 o/z sdram a10 address line. address line/autoprecharge disable for sdram memory. serves as a row address bit (logically equivalent to a12) during actv commands and also disables the autoprecharging function of sdram during read or write operations. emif.sda10 is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk output, emif.sda10 gpio0 = 0: input, gpio13 gpio13 i/o/z general-purpose io13. gpio13 is selected when the parallel port mode bit field is set to 10 or 11. c14 i/o/z memory interface clock for sdram, hpi data strobe 2 input, or general-purpose io14. this pin serves in one of two functions: memory interface clock for sdram (emif.clkmem) or hpi data strobe 2 (hpi.hds2 ). the initial state of this pin depends on the gpio0 pin. see section 3.5.1 for more information. gpio0 = 1: output, emif.clkmem emif.clkmem o/z memory interface clock for sdram. emif.clkmem is selected when the parallel port mode bit field of the external bus selection register is set to 00 or 01. bk emif.clkmem gpio0 = 0: input, hpi.hds2 i hpi data strobe 2 input. hpi.hds2 is driven by the host read or write strobes to control the transfer. hpi.hds2 is selected when the parallel port mode bit field is set to 10 or 11. input, hpi.hds2 ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 23 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name interrupt and reset pins int[4:0] i active-low external user interrupt inputs. int[4:0] are maskable and are prioritized by the interrupt enable register (ier) and the interrupt mode bit. h, fs input reset i active-low reset. reset causes the digital signal processor (dsp) to terminate execution and forces the program counter to ff8000h. when reset is brought to a high level, execution begins at location ff8000h of program memory. reset affects various registers and status bits. use an external pullup resistor on this pin. h, fs input bit i/o signals gpio[7:6,4:0] (lqfp) gpio[7:0] (bga) i/o/z 7-bit (lqfp package) or 8-bit (bga package) input/output lines that can be individually configured as inputs or outputs, and also individually set or reset when configured as outputs. at reset, these pins are configured as inputs. after reset, the on-chip bootloader samples gpio[3:0] to determine the boot mode selected. bk (gpio5 only) h input emif.cke (gpio4) o/z sdram cke signal. the gpio4 pin can be configured to serve as sdram cke pin by setting the following bits in the external bus selection register: cke sel = 1 and cke en = 1. in default mode, this pin serves as gpio4. h (except gpio5) input (gpio4) xf o/z external flag. xf is set high by the bset xf instruction, set low by bclr xf instruction or by loading st1. xf is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. xf goes into the high-impedance state when off is low, and is set high following reset. output emif.cke o/z sdram cke signal. the xf pin can be configured to serve as sdram cke pin by setting the following bits in the external bus selection register: cke sel = 0 and cke en = 1. in default mode, this pin serves as xf. output (xf) oscillator/clock signals clkout o/z dsp clock output signal. clkout cycles at the machine-cycle rate of the cpu. clkout goes into high-impedance state when off is low. output x2/clkin i/o system clock/oscillator input. if the internal oscillator is not being used, x2/clkin functions as the clock input. note: in clkgen domain idle (osc idle) mode, this pin becomes output and is driven low to stop external crystals (if used) from oscillating or an external clock source from driving the dsp?s internal logic. oscillator input x1 o output pin from the internal system oscillator for the crystal. if the internal oscillator is not used, x1 should be left unconnected. x1 does not go into the high-impedance state when off is low. oscillator output ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 24 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name timer signals tin/tout0 i/o/z timer0 input/output. when output, tin/tout0 signals a pulse or a change of state when the on-chip timer counts down past zero. when input, tin/tout0 provides the clock source for the internal timer module. at reset, this pin is configured as an input. note: only the timer0 signal is brought out. the timer1 signal is terminated internally and is not available for external use. h input real-time clock rtcinx1 i real-time clock oscillator input input rtcinx2 o real-time clock oscillator output output i 2 c sda i/o/z i 2 c (bidirectional) data. at reset, this pin is in high-impedance mode. h hi-z scl i/o/z i 2 c (bidirectional) clock. at reset, this pin is in high-impedance mode. h hi-z multichannel buffered serial ports signals clkr0 i/o/z mcbsp0 receive clock. clkr0 serves as the serial shift clock for the serial port receiver. at reset, this pin is in high-impedance mode. h hi-z dr0 i mcbsp0 receive data fs input fsr0 i/o/z mcbsp0 receive frame synchronization. the fsr0 pulse initiates the data receive process over dr0. at reset, this pin is in high-impedance mode. hi-z clkx0 i/o/z mcbsp0 transmit clock. clkx0 serves as the serial shift clock for the serial port transmitter. the clkx0 pin is configured as input after reset. h input dx0 o/z mcbsp0 transmit data. dx0 is placed in the high-impedance state when not transmitting, when reset is asserted, or when off is low. hi-z fsx0 i/o/z mcbsp0 transmit frame synchronization. the fsx0 pulse initiates the data transmit process over dx0. configured as an input following reset. input clkr1 i/o/z mcbsp1 receive clock. clkr1 serves as the serial shift clock for the serial port receiver. h input dr1 i/z mcbsp1 serial data receive input fsr1 i/z mcbsp1 receive frame synchronization. the fsr1 pulse initiates the data receive process over dr1. input dx1 o/z mcbsp1 serial data transmit. dx1 is placed in the high-impedance state when not transmitting, when reset is asserted, or when off is low. bk hi-z clkx1 i/o/z mcbsp1 transmit clock. clkx1 serves as the serial shift clock for the serial port transmitter. the clkx1 pin is configured as input after reset. h input fsx1 i/o/z mcbsp1 transmit frame synchronization. the fsx1 pulse initiates the data transmit process over dx1. configured as an input following reset. input ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 25 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name multichannel buffered serial ports signals (continued) clkr2 i/o/z mcbsp2 receive clock. clkr2 serves as the serial shift clock for the serial port receiver. h input dr2 i mcbsp2 serial data receive input fsr2 i mcbsp2 receive frame synchronization. the fsr2 pulse initiates the data receive process over dr2. input dx2 o/z mcbsp2 serial data transmit. dx2 is placed in the high-impedance state when not transmitting, when reset is asserted, or when off is low. bk hi-z clkx2 i/o/z mcbsp2 transmit clock. clkx2 serves as the serial shift clock for the serial port transmitter. the clkx2 pin is configured as input after reset. h input fsx2 i/o/z mcbsp2 frame synchronization. the fsx2 pulse initiates the data transmit process over dx2. fsx2 is configured as an input following reset. input test/emulation pins tck i ieee standard 1149.1 test clock. tck is normally a free-running clock signal with a 50% duty cycle. the changes on test access port (tap) of input signals tms and tdi are clocked into the tap controller, instruction register, or selected test data register on the rising edge of tck. changes at the tap output signal (tdo) occur on the falling edge of tck. pu h input tdi i ieee standard 1149.1 test data input. pin with internal pullup device. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. pu input tdo o/z ieee standard 1149.1 test data output. the contents of the selected register (instruction or data) are shifted out of tdo on the falling edge of tck. tdo is in the high-impedance state except when the scanning of data is in progress. hi-z tms i ieee standard 1149.1 test mode select. pin with internal pullup device. this serial control input is clocked into the tap controller on the rising edge of tck. pu input trst i ieee standard 1149.1 test reset. trst , when high, gives the ieee standard 1149.1 scan system control of the operations of the device. if trst is not connected or driven low, the device operates in its functional mode, and the ieee standard 1149.1 signals are ignored. this pin has an internal pulldown. pd fs input emu0 i/o/z emulator 0 pin. when trst is driven low, emu0 must be high for activation of the off condition. when trst is driven high, emu0 is used as an interrupt to or from the emulator system and is defined as i/o by way of the ieee standard 1149.1 scan system. pu input emu1/off i/o/z emulator 1 pin/disable all outputs. when trst is driven high, emu1/off is used as an interrupt to or from the emulator system and is defined as i/o by way of ieee standard 1149.1 scan system. when trst is driven low, emu1/off is configured as off . the emu1/off signal, when active-low, puts all output drivers into the high-impedance state. note that off is used exclusively for testing and emulation purposes (not for multiprocessing applications). therefore, for the off condition, the following apply: trst = low, emu0 = high, emu1/off = low pu input ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
introduction 26 april 2004 ? revised january 2008 sprs245j table 2?3. signal descriptions (continued) terminal name reset condition bk ? function i/o/z ? multiplexed signal name supply pins cv dd s digital power, + v dd . dedicated power supply for the core cpu. dv dd s digital power, + v dd . dedicated power supply for the i/o pins. rdv dd s digital power, + v dd . dedicated power supply for the i/o pins of the rtc module. rcv dd s digital power, + v dd . dedicated power supply for the rtc module v ss s digital ground. dedicated ground for the i/o and core pins. reserved rsvd1 reserved. must be pulled up. use 10-k ? resistor. rsvd2 reserved. must be pulled low. use 10-k ? resistor. miscellaneous nc no connection ? i = input, o = output, s = supply, hi-z = high-impedance ? bk = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), pu = pullup, pd = pulldown, h = hysteresis input buffer, fs = fail-safe buffer
functional overview 27 april 2004 ? revised january 2008 sprs245j 3 functional overview the following functional overview is based on the block diagram in figure 3?1. ? ? 7/8 5 ? number of pins determined by package type. figure 3?1. block diagram of the tms320vc5503
functional overview 28 april 2004 ? revised january 2008 sprs245j 3.1 memory the 5503 supports a unified memory map (program and data accesses are made to the same physical space). the total on-chip memory is 128k bytes (32k 16-bit words of ram and 32k 16-bit words of rom). 3.1.1 on-chip dual-access ram (daram) the daram is located in the byte address range 000000h?00ffffh and is composed of eight blocks of 8k bytes each (see table 3?1). each daram block can perform two accesses per cycle (two reads, two writes, or a read and a write). daram can be accessed by the internal program, data, or dma buses. the hpi can only access the first four (32k bytes) daram blocks. table 3?1. daram blocks byte address range memory block 000000h ? 001fffh daram 0 (hpi accessible) ? 002000h ? 003fffh daram 1 (hpi accessible) 004000h ? 005fffh daram 2 (hpi accessible) 006000h ? 007fffh daram 3 (hpi accessible) 008000h ? 009fffh daram 4 00a000h ? 00bfffh daram 5 00c000h ? 00dfffh daram 6 00e000h ? 00ffffh daram 7 ? first 192 bytes are reserved for memory-mapped registers (mmrs). 3.1.2 on-chip read-only memory (rom) the one-wait-state rom is located at the byte address range ff0000h?ffffffh, for a total of 64k bytes of rom. the rom address space can be mapped by software to the external memory or to the internal rom. the standard 5503 device includes a bootloader program resident in the rom. when the mpnmc bit field of the st3 status register is set through software, the on-chip rom is disabled and not present in the memory map, and byte address range ff0000h?ffffffh is directed to external memory space. a hardware reset always clears the mpnmc bit, so it is not possible to disable the rom at reset. however, the software reset instruction does not affect the mpnmc bit. the on-chip rom can be accessed by the program, data, or dma buses. the first 16-bit word access to rom requires three cycles. subsequent accesses require two cycles per 16-bit word.
functional overview 29 april 2004 ? revised january 2008 sprs245j 3.1.3 memory maps 3.1.3.1 pge package memory map the pge package features 14 address bits representing 32k-/16k-byte linear address for asynchronous memories per ce space. due to address row/column multiplexing, address reach for sdram devices is 4m bytes for each ce space. the largest sdram device that can be used with the 5503 in a pge package is 128m-bit sdram. 000000 daram / hpi access (32k ? 192) bytes 008000 daram ? 32k bytes 010000 external ? ce0 040000 400000 800000 c00000 ff0000 64k bytes f fffff external ? ce1 external ? ce2 external ? ce3 block size byte address (hex) ? (if mpnmc=0) rom # (if mpnmc=1) external ? ce3 32k/16k bytes ? asynchronous 4m bytes ? sdram (mpnmc = 1) 4m bytes ? 64k bytes if internal rom selected (mpnmc = 0) 32k/16k bytes ? asynchronous 4m bytes ? sdram 32k/16k bytes ? asynchronous 4m bytes ? sdram 32k/16k bytes ? asynchronous 4m bytes ? 64k bytes sdram ? memory blocks ? address shown represents the first byte address in each block. ? dual-access ram (daram): two accesses per cycle per block, 8 blocks of 8k bytes. external memory spaces are selected by the chip-enable signal shown (ce[0:3] ). supported memory types include: asynchronous static ram (sram) and synchronous dram (sdram). ? the minus 64k bytes consists of 32k-byte daram/hpi access and 32k-byte daram. # read-only memory (rom): one access every two cycles. 32k bytes for 16-bit-wide memory. 16k bytes for 8-bit-wide memory. 0000c0 mmr (reserved) reserved figure 3?2. tms320vc5503 memory map (pge package)
functional overview 30 april 2004 ? revised january 2008 sprs245j 3.1.3.2 ghh and zhh package(s) memory map the ghh and zhh packages feature 21 address bits representing 2m-byte linear address for asynchronous memories per ce space. due to address row/column multiplexing, address reach for sdram devices is 4m bytes for each ce space. the largest sdram device that can be used with the 5503 in a ghh and zhh package is 128m-bit sdram. 000000 daram / hpi access (32k ? 192) bytes 008000 daram ? 32k bytes 010000 external ? ce0 040000 400000 800000 c00000 ff0000 64k bytes f fffff external ? ce1 external ? ce2 external ? ce3 block size byte address (hex) ? (if mpnmc=0) rom # (if mpnmc=1) external ? ce3 2m bytes ? asynchronous 4m bytes ? sdram (mpnmc = 1) 4m bytes ? 64k bytes if internal rom selected (mpnmc = 0) 2m bytes ? asynchronous 4m bytes ? sdram 2m bytes ? asynchronous 4m bytes ? sdram 2m bytes ? asynchronous 4m bytes ? 64k bytes sdram ? memory blocks ? address shown represents the first byte address in each block. ? dual-access ram (daram): two accesses per cycle per block, 8 blocks of 8k bytes. external memory spaces are selected by the chip-enable signal shown (ce[0:3] ). supported memory types include: asynchronous static ram (sram) and synchronous dram (sdram). ? the minus 64k bytes consists of 32k-byte daram/hpi access and 32k-byte daram. # read-only memory (rom): one access every two cycles. 0000c0 mmr (reserved) reserved figure 3?3. tms320vc5503 memory map (ghh and zhh packages)
functional overview 31 april 2004 ? revised january 2008 sprs245j 3.1.4 boot configuration the on-chip bootloader provides a method to transfer application code and tables from an external source to the on-chip ram memory at power up. these options include: ? enhanced host-port interface (hpi) in multiplexed or nonmultiplexed mode ? external asynchronous memory boot (via the emif) from 8-bit-wide or 16-bit-wide memory ? serial port boot (from mcbsp0) with 8-bit or 16-bit data length ? serial eprom boot (from mcbsp0) supporting eproms with 16-bit or 24-bit address ? i 2 c eeprom ? direct execution from external 16-bit-wide asynchronous memory external pins select the boot configuration. the values of gpio[3:0] are sampled, following reset, upon execution of the on-chip bootloader code. it is not possible to disable the bootloader at reset because the 5503 always starts execution from the on-chip rom following a hardware reset. a summary of boot configurations is shown in table 3?2. for more information on using the bootloader, see the using the tms320vc5503/vc5507/vc5509/vc5509a bootloader application report (literature number spra375). table 3?2. boot configuration summary gpio0 gpio3 gpio2 gpio1 boot mode process 0 0 0 0 reserved 0 0 0 1 serial (spi) eprom boot (24-bit address) via mcbsp0 0 0 1 0 reserved 0 0 1 1 i 2 c eeprom (7-bit address) 0 1 0 0 reserved 0 1 0 1 hpi ? multiplexed mode 0 1 1 0 hpi ? nonmultiplexed mode 0 1 1 1 reserved 1 0 0 0 execute from 16-bit-wide asynchronous memory (on ce1 space) 1 0 0 1 serial (spi) eprom boot (16-bit address) via mcbsp0 1 0 1 0 8-bit asynchronous memory (on ce1 space) 1 0 1 1 16-bit asynchronous memory (on ce1 space) 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 standard serial boot via mcbsp0 (16-bit data) 1 1 1 1 standard serial boot via mcbsp0 (8-bit data)
functional overview 32 april 2004 ? revised january 2008 sprs245j 3.2 peripherals the 5503 supports the following peripherals: ? a configurable parallel external interface supporting either: ? 16-bit external memory interface (emif) for asynchronous memory and/or sdram ? 16-bit enhanced host-port interface (hpi) ? a six-channel direct memory access (dma) controller ? a programmable phase-locked loop clock generator ? two 20-bit timers ? watchdog timer ? three multichannel buffered serial ports (mcbsps) ? seven (lqfp) or eight (bga) configurable general-purpose i/o pins ? i 2 c multi-master and slave interface (i 2 c compatible except, no fail-safe i/o buffers) ? real-time clock with crystal input, separate clock domain and supply pins for detailed information on the c55x ? dsp peripherals, see the following documents: ? tms320c55x ? dsp functional overview (literature number spru312) ? tms320c55x dsp peripherals overview reference guide (literature number spru317) 3.3 direct memory access (dma) controller the 5503 dma provides the following features: ? three standard ports, one for each of the following data resources: daram, peripherals, and external memory ? six channels, which allow the dma controller to track the context of six independent dma channels ? programmable low/high priority for each dma channel ? one interrupt for each dma channel ? event synchronization. dma transfers in each channel can be dependent on the occurrence of selected events. ? programmable address modification for source and destination addresses ? dedicated idle domain allows the dma controller to be placed in a low-power (idle) state under software control. ? dedicated dma channel used by the hpi to access internal memory (daram) the 5503 dma controller allows transfers to be synchronized to selected events. the 5503 supports 15 separate sync events and each channel can be tied to separate sync events independent of the other channels. sync events are selected by programming the sync field in the channel-specific dma channel control register (dma_ccr).
functional overview 33 april 2004 ? revised january 2008 sprs245j 3.3.1 dma channel control register (dma_ccr) the channel control register (dma_ccr) bit layouts are shown in figure 3?4. 15 14 13 12 11 10 9 8 dst amode src amode end prog reserved repeat auto init r/w, 00 r/w, 00 r/w, 0 r, 0 r/w, 0 r/w, 0 7654 0 en prio fs sync r/w, 0 r/w, 0 r/w, 0 r/w, 00000 legend: r = read, w = write, n = value after reset figure 3?4. dma_ccr bit locations the sync[4:0] bits specify the event that can initiate the dma transfer for the corresponding dma channel. the five bits allow several configurations as listed in table 3?3. the bits are set to zero upon reset. for those synchronization modes with more than one peripheral listed, the serial port mode bit field of the external bus selection register dictates which peripheral event is actually connected to the dma input. table 3?3. synchronization control function sync field in dma_ccr synchronization mode 00000b no event synchronized 00001b mcbsp 0 receive event (revt0) 00010b mcbsp 0 transmit event (xevt0) 00011b reserved. these bits should always be written with 0. 00100b reserved. these bits should always be written with 0. 00101b mcbsp1 receive event (revt1) 00110b mcbsp1 transmit event (xevt1) 00111b reserved. these bits should always be written with 0. 01000b reserved. these bits should always be written with 0. 01001b mcbsp2 receive event (revt2) 01010b mcbsp2 transmit event (xevt2) 01011b reserved. these bits should always be written with 0. 01100b reserved. these bits should always be written with 0. 01101b timer 0 interrupt event 01110b timer 1 interrupt event 01111b external interrupt 0 10000b external interrupt 1 10001b external interrupt 2 10010b external interrupt 3 10011b external interrupt 4 / i 2 c receive event (revti2c) ? 10100b i 2 c transmit event (xevti2c) other values reserved (do not use these values) ? the i 2 c receive event (revti2c) and external interrupt 4 (int4) share a synchronization input to the dma. when the sync field of the dma_ccr is set to 10011b, the logical or of these two sources is used for dma synchronization.
functional overview 34 april 2004 ? revised january 2008 sprs245j 3.4 i 2 c interface the tms320vc5503 includes an i 2 c serial port. the i 2 c port supports: ? compatible with philips i 2 c specification revision 2.1 (january 2000) ? operates at 100 kbps or 400 kbps ? 7-bit addressing mode ? master (transmit/receive) and slave (transmit/receive) modes of operation ? events: dma, interrupt, or polling the i 2 c module clock must be in the range from 7 mhz to 12 mhz. this is necessary for proper operation of the i 2 c module. with the i 2 c module clock in this range, the noise filters on the sda and scl pins suppress noise that has a duration of 50 ns or shorter. the i 2 c module clock is derived from the dsp clock divided by a programmable prescaler. note: i/o buffers are not fail-safe. the sda and scl pins could potentially draw current if the device is powered down and sda and scl are driven by other devices connected to the i 2 c bus. 3.5 configurable external buses the 5503 offers combinations of configurations for its external parallel port. this allows the system designer to choose the appropriate media interface for its application without the need of a large-pin-count package. the external bus selection register controls the routing of the parallel port signals.
functional overview 35 april 2004 ? revised january 2008 sprs245j 3.5.1 external bus selection register (ebsr) the external bus selection register determines the mapping of the 14 (lqfp) or 21 (bga) address signals, 16 data signals, and 15 control signals of the external parallel port. the external bus selection register is memory-mapped at port address 0x6c00. once the bit fields of this register are changed, the routing of the signals takes place on the next cpu clock cycle. the reset value of the parallel port mode bit field is determined by the state of the gpio0 pin at reset. if gpio0 is high at reset, the full emif mode is enabled and the parallel port mode bit field is set to 01. if gpio0 is low at reset, the hpi multiplexed mode is enabled and the parallel port mode bit field is set to 11. after reset, the parallel port should be selected to function in either emif mode or hpi mode. dynamic switching of the parallel port, once configured, is not recommended. 15 14 13 12 11 10 9 8 clkout disable osc disable hidl bke sr stat hold holda cke sel r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 1 r/w, 0 7 6 5 2 1 0 cke en sr cmd reserved (see note) parallel port mode r/w, 0 r/w, 0 r, 0000 r/w, 01 if gpio0 = 1 11 if gpio0 = 0 legend: r = read, w = write, n = value after reset note: these bits are reserved and must be kept as 0000 during any writes to ebsr. figure 3?5. external bus selection register table 3?4. external bus selection register bit field description bits description 15 clkout disable. clkout disable = 0: clkout enabled clkout disable = 1: clkout disabled 14 oscillator disable. works with idle instruction to put the clock generation domain into idle mode. osc disable = 0: oscillator enabled osc disable = 1: oscillator disabled 13 host mode idle bit. (applicable only if the parallel bus is configured as ehpi.) when the parallel bus is set to ehpi mode, the clock domain is not allowed to go to idle, so a host processor can access the dsp internal memory. the hidl bit works around this restriction and allows the dsp to idle the clock domain and the ehpi. when the clock domain is in idle, a host processor will not be able to access the dsp memory. hidl = 0: host access to dsp enabled. idling ehpi and clock domain is not allowed. hidl = 1: idles the hpi and the clock domain upon execution of the idle instruction when the parallel port mode is set to 10 or 11 selecting hpi mode. in addition, bit 4 of the idle control register must be set to 1 prior to the execution of the idle instruction. 12 bus keeper enable. ? bke = 0: bus keeper, pullups/pulldowns enabled bke = 1: bus keeper, pullups/pulldowns disabled 11 sdram self-refresh status bit. sr stat = 0: sdram self-refresh signal is not asserted . sr stat = 1: sdram self-refresh signal is asserted ? function available when the port or pins configured as input.
functional overview 36 april 2004 ? revised january 2008 sprs245j table 3?4. external bus selection register bit field description (continued) bits description 10 emif hold hold = 0: dsp drives the external memory bus hold = 1: request the external memory bus to be placed in high-impedance so that another device can drive the memory bus 9 emif hold acknowledge. holda = 0: dsp indicates that a hold request on the external memory bus has occured, the emif completed any pending external bus activity, and placed the external memory bus signals in high-impedance state (address bus, data bus, ce[3:0] , aoe , awe, are , sdras , sdcas , sdwe , sda10, clkmem). once this bit is cleared, an external device can drive the bus. holda = 1: no hold acknowledge 8 sdram cke pin selection bit. cke sel = 0: use xf for sdram cke signal cke sel = 1: use gpio.4 for sdram cke signal 7 sdram cke enable bit. cke en = 0: xf or gpio.4 operates in normal mode cke en = 1: based on the cke sel bit, either xf or gpio.4 drives the sdram cke pin 6 sdram self-refresh command. sr cmd = 0: emif will not issue a sdram self-refresh command sr cmd = 1: emif will issue a sdram self-refresh command 5?2 reserved. must be kept as 0000 during any writes to ebsr. 1?0 parallel port mode. emif/hpi/gpio mode. determines the mode of the parallel port . parallel port mode = 00: data emif mode. the 16 emif data signals and 13 emif control signals are routed to the corresponding external parallel bus data and control signals. the 14 (lqfp) or 16 (bga) address bus signals can be used as general-purpose i/o only. parallel port mode = 01: full emif mode. the 14 (lqfp) or 21 (bga) address signals , 16 data signals, and 15 control signals are routed to the corresponding external parallel bus address, data, and control signals. parallel port mode = 10: non-multiplexed hpi mode. the hpi is enabled an its 14 address signals, 16 data signals, and 7 control signals are routed to the corresponding address, data, control signals of the external parallel bus. moreover, 8 control signals of the external parallel bus are used as general-purpose i/o. parallel port mode = 11: multiplexed hpi mode. the hpi is enabled and its 16 data signals and 10 control signals are routed to the external parallel bus. in addition, 3 control signals of the external parallel bus are used as general-purpose i/o. the 14 (lqfp) or 16 (bga) external parallel port address bus signals are used as general-purpose i/o. ? function available when the port or pins configured as input.
functional overview 37 april 2004 ? revised january 2008 sprs245j 3.5.2 parallel port the parallel port of the 5503 consists of 14 (lqfp) or 21 (bga) address signals, 16 data signals, and 15 control signals. its 14 bits for address allow it to access 16k (lqfp) or 2m bytes of external memory when using the asynchronous sram interface. on the other hand, the sdram interface can access the whole external memory space of 16m bytes. the parallel bus supports four different modes: ? full emif mode: the emif with its 14 (lqfp) or 21 address signals, 16 data signals, and 15 control signals routed to the corresponding external parallel bus address, data, and control signals. ? data emif mode: the emif with its 16 data signals, and 15 control signals routed to the corresponding external parallel bus data and control signals. the 14 (lqfp) or 16 (bga) address bus signals can be used as general-purpose i/o signals only. ? non-multiplexed hpi mode: the hpi is enabled with its 14 address signals, 16 data signals, and 8 control signals routed to the corresponding address, data, and control signals of the external parallel bus. moreover, 7 control signals of the external parallel bus are used as general-purpose i/o. ? multiplexed hpi mode: the hpi is enabled with its 16 data signals and 10 control signals routed to the external parallel bus. in addition, 5 control signals of the external parallel bus are used as general-purpose i/o. the external parallel port?s 14 (lqfp) or 16 (bga) address signals are used as general-purpose i/o. table 3?5. tms320vc5503 parallel port signal routing pin signal data emif (00) ? full emif (01) ? non-multiplex hpi (10) ? multiplex hpi (11) ? address bus a?[0] n/a emif.a[0] (bga) n/a n/a a[0] gpio.a[0] (lqfp) emif.a[0] (lqfp) hpi.ha[0] (lqfp) gpio.a[0] (lqfp) a[0] gpio.a[0] (bga) hpi.ha[0] (bga) gpio.a[0] (bga) a[13:1] gpio.a[13:1] (lqfp) emif.a[13:1] (lqfp) hpi.ha[13:1] (lqfp) gpio.a[13:1] (lqfp) a[13:1] gpio.a[13:1] (bga) emif.a[13:1] (bga) hpi.ha[13:1] (bga) gpio.a[13:1] (bga) a[15:14] gpio.a[15:14] (bga) emif.a[15:14] (bga) n/a gpio.a[15:14] (bga) a[20:16] ? n/a emif.a[20:16] (bga) n/a n/a data bus d[15:0] emif.d[15:0] emif.d[15:0] hpi.hd[15:0] hpi.hd[15:0] control bus c0 emif.are emif.are gpio8 gpio8 c1 emif.aoe emif.aoe hpi.hint hpi.hint c2 emif.awe emif.awe hpi.hr/w hpi.hr/w c3 emif.ardy emif.ardy hpi.hrdy hpi.hrdy c4 emif.ce0 emif.ce0 gpio9 gpio9 c5 emif.ce1 emif.ce1 gpio10 gpio10 c6 emif.ce2 emif.ce2 hpi.hcntl0 hpi.hcntl0 c7 emif.ce3 emif.ce3 gpio11 hpi.hcntl1 c8 emif.be0 emif.be0 hpi.hbe0 hpi.hbe0 c9 emif.be1 emif.be1 hpi.hbe1 hpi.hbe1 c10 emif.sdras emif.sdras gpio12 hpi.has c11 emif.sdcas emif.sdcas hpi.hcs hpi.hcs c12 emif.sdwe emif.sdwe hpi.hds1 hpi.hds1 c13 emif.sda10 emif.sda10 gpio13 gpio13 c14 emif.clkmem emif.clkmem hpi.hds2 hpi.hds2 ? represents the parallel port mode bits of the external bus selection register. ? a[20:16] of the bga package always functions as emif address pins and they cannot be reconfigured for any other function.
functional overview 38 april 2004 ? revised january 2008 sprs245j 3.5.3 parallel port signal routing the 5503 allows access to 16-bit-wide (read and write) or 8-bit-wide (read only) asynchronous memory and 16-bit-wide sdram. for 16-bit-wide memories, emif.a[0] is kept low and is not used. to provide as many address pins as possible, the 5503 routes the parallel port signals as shown in figure 3?6. figure 3?6 shows the addition of the a [0] signal in the bga package. this pin is used for asynchronous memory interface only, while the a[0] pin is used with hpi or gpio. figure 3?7 summarizes the use of the parallel port signals for memory interfacing. emif.a[0] gpio.a[0] hpi.ha[0] emif.a[13:1] hpi.ha[13:1] gpio.a[13:1] emif.a[14] gpio.a[14] emif.a[15] gpio.a[15] emif.a[20:16] a?[0] (bga only) a[0] a[13:1] a[14] (bga only) a[15] (bga only) a[20:16] (bga only) figure 3?6. parallel port signal routing
functional overview 39 april 2004 ? revised january 2008 sprs245j be[1:0] a[13:1] a[0] d[15:0] a[12:0] a[13] d[15:0] 16-bit asynchronous memory 5503 lqfp 16-bit-wide asynchronous memory bga 5503 a[20:14] d[15:0] a[13:1] be[1:0] 16-bit asynchronous memory d[15:0] a[19:13] a[12:0] bga 5503 a?[0] a[13:1] a[20:14] be[1:0] 8-bit-wide asynchronous memory 5503 lqfp a[13:0] d[7:0] memory asynchronous 8-bit a[0] a[13:1] a[20:14] be[1:0] memory asynchronous 8-bit a[13:0] d[7:0] d[7:0] d[7:0] 5503 lqfp clkmem sdcas sdras cex sdram 128 mbit 64 mbit or cas clk ras cs a[13] a[0] sdwe ba[0] ba[1] dqm[h:l] we a[12] sda10 a[10:1] d[15:0] a[11] a[9:0] d[15:0] a[10] 16-bit-wide sdram sdwe a[12] d[15:0] a[10:1] sda10 a[13] a[14] 5503 bga sdcas sdras clkmem cex we a[11] a[9:0] d[15:0] a[10] ba[1] ba[0] dqm[h:l] cas ras clk cs be[1:0] be[1:0] be[1:0] be[1:0] oe oe re re we we cex cs be[1:0] be[1:0] oe oe re re we we cex cs oe oe re re we we cex cs oe oe re re we we cex cs sdram 128 mbit 64 mbit or figure 3?7. parallel port (emif) signal interface
functional overview 40 april 2004 ? revised january 2008 sprs245j 3.6 general-purpose input/output (gpio) ports 3.6.1 dedicated general-purpose i/o the 5503 provides eight dedicated general-purpose input/output pins, gpio0?gpio7. each pin can be indepedently configured as an input or an output using the i/o direction register (iodir). the i/o data register (iodata) is used to monitor the logic state of pins configured as inputs and control the logic state of pins configured as outputs. see table 3?25 for address information. the description of the iodir is shown in figure 3?8 and table 3?6. the description of iodata is shown in figure 3?9 and table 3?7. to configure a gpio pin as an input, clear the direction bit that corresponds to the pin in iodir to 0. to read the logic state of the input pin, read the corresponding bit in iodata. to configure a gpio pin as an output, set the direction bit that co rresponds to the pin in iodir to 1. to control the logic state of the output pin, write to the corresponding bit in iodata. 15 876543210 reserved io7dir io6dir io5dir (bga) io4dir io3dir io2dir io1dir io0dir r?00000000 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 legend: r = read, w = write, n = value after reset figure 3?8. i/o direction register (iodir) bit layout table 3?6. i/o direction register (iodir) bit functions bit no. bit name reset value function 15?8 reserved 0 these bits are reserved and are unaffected by writes. 7?0 ioxdir ? 0 iox direction control bit. controls whether iox operates as an input or an output. ioxdir = 0 iox is configured as an input. ioxdir = 1 iox is configured as an output. ? the gpio5 pin is available on the bga package only.
functional overview 41 april 2004 ? revised january 2008 sprs245j 15 876543210 reserved io7d io6d io5d (bga) io4d io3d io2d io1d io0d r?00000000 r/w?pin r/w?pin r/w?pin r/w?pin r/w?pin r/w?pin r/w?pin r/w?pin legend: r = read, w = write, pin = value present on the pin (io7?io0 default to inputs after reset) figure 3?9. i/o data register (iodata) bit layout table 3?7. i/o data register (iodata) bit functions bit no. bit name reset value function 15?8 reserved 0 these bits are reserved and are unaffected by writes. 7?0 ioxd pin ?? iox data bit. if iox is configured as an input (ioxdir = 0 in iodir): ioxd = 0 the signal on the iox pin is low. ioxd = 1 the signal on the iox pin is high. if iox is configured as an output (ioxdir = 1 in iodir): ioxd = 0 drive the signal on the iox pin low. ioxd = 1 drive the signal on the iox pin high. ? the gpio5 pin is available on the bga package only. ? pin = value present on the pin (io7?io0 default to inputs after reset) 3.6.2 address bus general-purpose i/o the 16 address signals, emif.a[15?0], can also be individually enabled as gpio when the parallel port mode bit field of the external bus selection register is set for data emif (00) or multiplexed ehpi mode (11). these pins are controlled by three registers: the enable register, agpioen, determines if the pins serve as gpio or address (figure 3?10); the direction register, agpiodir, determines if the gpio enabled pin is an input or output (figure 3?11); and the data register, agpiodata, determines the logic states of the pins in general-purpose i/o mode (figure 3?12). 15 14 13 12 11 10 9 8 aioen15 (bga) aioen14 (bga) aioen13 aioen12 aioen11 aioen10 aioen9 aioen8 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 76543210 aioen7 aioen6 aioen5 aioen4 aioen3 aioen2 aioen1 aioen0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?10. address/gpio enable register (agpioen) bit layout table 3?8. address/gpio enable register (agpioen) bit functions bit no. bit name reset value function 15?0 aioenx 0 enable or disable gpio function of address bus of emif. aioen15 and aioen14 are only available in bga package. aioenx = 0 gpio function of ax line is disabled; i.e., ax has address function. aioenx = 1 gpio function of ax line is enabled; i.e., ax has gpio function.
functional overview 42 april 2004 ? revised january 2008 sprs245j 15 14 13 12 11 10 9 8 aiodir15 (bga) aiodir14 (bga) aiodir13 aiodir12 aiodir11 aiodir10 aiodir9 aiodir8 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 76543210 aiodir7 aiodir6 aiodir5 aiodir4 aiodir3 aiodir2 aiodir1 aiodir0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?11. address/gpio direction register (agpiodir) bit layout table 3?9. address/gpio direction register (agpiodir) bit functions bit no. bit name reset value function 15?0 aiodirx 0 data direction bits that configure the address bus configured as i/o pins as either input or output pins. aiodir15 and aiodir14 are only available in bga package. aiodirx = 0 configure corresponding pin as an input. aiodirx = 1 configure corresponding pin as an output. 15 14 13 12 11 10 9 8 aiod15 (bga) aiod14 (bga) aiod13 aiod12 aiod11 aiod10 aiod9 aiod8 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 76543210 aiod7 aiod6 aiod5 aiod4 aiod3 aiod2 aiod1 aiod0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?12. address/gpio data register (agpiodata) bit layout table 3?10. address/gpio data register (agpiodata) bit functions bit no. bit name reset value function 15?0 aiodx 0 data bits that are used to control the level of the address bus configured as i/o output pins, and to monitor the level of the address bus configured as i/o input pins. aiod15 and aiod14 are only available in bga package. if aiodirn = 0, then: aiodx = 0 corresponding i/o pin is read as a low. aiodx = 1 corresponding i/o pin is read as a high. if aiodirn = 1, then: aiodx = 0 set corresponding i/o pin to low. aiodx = 1 set corresponding i/o pin to high.
functional overview 43 april 2004 ? revised january 2008 sprs245j 3.6.3 ehpi general-purpose i/o six control lines of the external parallel bus can also be set as general-purpose i/o when the parallel port mode bit field of the external bus selection register is set to nonmultiplexed ehpi (10) or multiplexed ehpi mode (11). these pins are controlled by three registers: the enable register, ehpigpioen, determines if the pins serve as gpio or address (figure 3?13); the direction register, ehpigpiodir, determines if the gpio enabled pin is an input or output (figure 3?14); and the data register, ehpigpiodata, determines the logic states of the pins in gpio mode (figure 3?15). 15 6543210 reserved gpioen13 gpioen12 gpioen11 gpioen10 gpioen9 gpioen8 r, 0000 0000 00 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?13. ehpi gpio enable register (ehpigpioen) bit layout table 3?11. ehpi gpio enable register (ehpigpioen) bit functions bit no. bit name reset value function 15?6 reserved 0 reserved 5?0 gpioen13? gpioen8 0 enable or disable gpio function of ehpi control bus. gpioenx = 0 gpio function of gpiox line is disabled gpioenx = 1 gpio function of gpiox line is enabled 15 6543210 reserved gpiodir13 gpiodir12 gpiodir11 gpiodir10 gpiodir9 gpiodir8 r, 0000 0000 00 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?14. ehpi gpio direction register (ehpigpiodir) bit layout table 3?12. ehpi gpio direction register (ehpigpiodir) bit functions bit no. bit name reset value function 15?6 reserved 0 reserved 5?0 gpiodir13? gpiodir8 0 data direction bits that configure the ehpi control bus configured as i/o pins as either input or output pins. gpiodirx = 0 configure corresponding pin as an input. gpiodirx = 1 configure corresponding pin as an output.
functional overview 44 april 2004 ? revised january 2008 sprs245j 15 6543210 reserved gpiod13 gpiod12 gpiod11 gpiod10 gpiod9 gpiod8 r, 0000 0000 00 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 r/w, 0 legend: r = read, w = write, n = value after reset figure 3?15. ehpi gpio data register (ehpigpiodata) bit layout table 3?13. ehpi gpio data register (ehpigpiodata) bit functions bit no. bit name reset value function 15?6 reserved 0 reserved 5?0 gpiod13? gpiod8 0 data bits that are used to control the level of the ehpi control bus configured as i/o output pins, and to monitor the level of the ehpi control bus configured as i/o input pins. if gpiodirn = 0, then: gpiodx = 0 corresponding i/o pin is read as a low. gpiodx = 1 corresponding i/o pin is read as a high. if gpiodirn = 1, then: gpiodx = 0 set corresponding i/o pin to low. gpiodx = 1 set corresponding i/o pin to high.
functional overview 45 april 2004 ? revised january 2008 sprs245j 3.7 system register the system register (sysr) provides control over certain device-specific functions. the register is located at port address 07fdh. 15 8 reserved 7320 reserved clkdiv r/w legend: r = read, w = write, n = value after reset figure 3?16. system register bit locations table 3?14. system register bit fields bit function number name function 15?3 reserved these bits are reserved and are unaffected by writes. 2?0 clkdiv clkout divide factor. allows the clock present on the clkout pin to be a divided-down version of the internal cpu clock. this field does not affect the programming of the pll. clkdiv 000 = clkout represents the cpu clock divided by 1 clkdiv 001 = clkout represents the cpu clock divided by 2 clkdiv 010 = clkout represents the cpu clock divided by 4 clkdiv 011 = clkout represents the cpu clock divided by 6 clkdiv 100 = clkout represents the cpu clock divided by 8 clkdiv 101 = clkout represents the cpu clock divided by 10 clkdiv 110 = clkout represents the cpu clock divided by 12 clkdiv 111 = clkout represents the cpu clock divided by 14
functional overview 46 april 2004 ? revised january 2008 sprs245j 3.8 memory-mapped registers the 5503 has 78 memory-mapped cpu registers that are mapped in data memory space address 0h to 4fh. table 3?15 provides a list of the cpu memory-mapped registers (mmrs) available. the corresponding tms320c54x ? (c54x ? ) cpu registers are also indicated where applicable. table 3?15. cpu memory-mapped registers c55x register c54x register word address (hex) description bit field ier0 imr 00 interrupt enable register 0 [15?0] ifr0 ifr 01 interrupt flag register 0 [15?0] st0_55 ? 02 status register 0 for c55x [15?0] st1_55 ? 03 status register 1 for c55x [15?0] st3_55 ? 04 status register 3 for c55x [15?0] ? ? 05 reserved [15?0] st0 st0 06 status register st0 [15?0] st1 st1 07 status register st1 [15?0] ac0l al 08 accumulator 0 [15?0] ac0h ah 09 [31?16] ac0g ag 0a [39?32] ac1l bl ob accumulator 1 [15?0] ac1h bh 0c [31?16] ac1g bg 0d [39?32] t3 treg 0e temporary register [15?0] trn0 trn 0f transition register [15?0] ar0 ar0 10 auxiliary register 0 [15?0] ar1 ar1 11 auxiliary register 1 [15?0] ar2 ar2 12 auxiliary register 2 [15?0] ar3 ar3 13 auxiliary register 3 [15?0] ar4 ar4 14 auxiliary register 4 [15?0] ar5 ar5 15 auxiliary register 5 [15?0] ar6 ar6 16 auxiliary register 6 [15?0] ar7 ar7 17 auxiliary register 7 [15?0] sp sp 18 stack pointer register [15?0] bk03 bk 19 circular buffer size register [15?0] brc0 brc 1a block repeat counter [15?0] rsa0l rsa 1b block repeat start address [15?0] rea0l rea 1c block repeat end address [15?0] pmst pmst 1d processor mode status register [15?0] xpc xpc 1e program counter extension register [7?0] ? ? 1f reserved [15?0] t0 ? 20 temporary data register 0 [15?0] t1 ? 21 temporary data register 1 [15?0] t2 ? 22 temporary data register 2 [15?0] t3 ? 23 temporary data register 3 [15?0] ac2l ? 24 accumulator 2 [15?0] ac2h ? 25 [31?16] ac2g ? 26 [39?32] tms320c54x and c54x are trademarks of texas instruments.
functional overview 47 april 2004 ? revised january 2008 sprs245j table 3?15. cpu memory-mapped registers (continued) c55x register bit field description word address (hex) c54x register cdp ? 27 coefficient data pointer [15?0] ac3l ? 28 accumulator 3 [15?0] ac3h ? 29 [31?16] ac3g ? 2a [39?32] dph ? 2b extended data page pointer [6?0] mdp05 ? 2c reserved [6?0] mdp67 ? 2d reserved [6?0] dp ? 2e memory data page start address [15?0] pdp ? 2f peripheral data page start address [8?0] bk47 ? 30 circular buffer size register for ar[4?7] [15?0] bkc ? 31 circular buffer size register for cdp [15?0] bsa01 ? 32 circular buffer start address register for ar[0?1] [15?0] bsa23 ? 33 circular buffer start address register for ar[2?3] [15?0] bsa45 ? 34 circular buffer start address register for ar[4?5] [15?0] bsa67 ? 35 circular buffer start address register for ar[6?7] [15?0] bsac ? 36 circular buffer coefficient start address register [15?0] bios ? 37 data page pointer storage location for 128-word data table [15?0] trn1 ? 38 transition register 1 [15?0] brc1 ? 39 block repeat counter 1 [15?0] brs1 ? 3a block repeat save 1 [15?0] csr ? 3b computed single repeat [15?0] rsa0h ? 3c repeat start address 0 [23?16] rsa0l ? 3d [15?0] rea0h ? 3e repeat end address 0 [23?16] rea0l ? 3f [15?0] rsa1h ? 40 repeat start address 1 [23?16] rsa1l ? 41 [15?0] rea1h ? 42 repeat end address 1 [23?16] rea1l ? 43 [15?0] rptc ? 44 repeat counter [15?0] ier1 ? 45 interrupt enable register 1 [15?0] ifr1 ? 46 interrupt flag register 1 [15?0] dbier0 ? 47 debug ier0 [15?0] dbier1 ? 48 debug ier1 [15?0] ivpd ? 49 interrupt vector pointer dsp [15?0] ivph ? 4a interrupt vector pointer host [15?0] st2_55 ? 4b status register 2 for c55x [15?0] ssp ? 4c system stack pointer [15?0] sp ? 4d user stack pointer [15?0] sph ? 4e extended data page pointer for the sp and the ssp [6?0] cdph ? 4f main data page pointer for the cdp [6?0]
functional overview 48 april 2004 ? revised january 2008 sprs245j 3.9 peripheral register description each 5503 device has a set of memory-mapped registers associated with peripherals as listed in table 3?16 through table 3?29. some registers use less than 16 bits. when reading these registers, unused bits are always read as 0. note: the cpu access latency to the peripheral memory-mapped registers is 6 cpu cycles. following peripheral register update(s), the cpu must wait at least 6 cpu cycles before attempting to use that peripheral. when more than one peripheral register is updated in a sequence, the cpu only needs to wait following the final register write. for example, if the emif is being reconfigured, the cpu must wait until the very last emif register update takes effect before trying to access the external memory. the users should consult the respective peripheral user?s guide to determine if a peripheral requires additional time to initialize itself to the new configuration after the register updates take effect. table 3?16. idle control, status, and system registers word address register name description reset value ? 0x0001 icr[7:0] idle control register xxxx xxxx 0000 0100 0x0002 istr[7:0] idle status register xxxx xxxx 0000 0000 0x07fd sysr[15:0] system register 0000 0000 0000 0000 ? hardware reset; x denotes a ?don?t care.? table 3?17. external memory interface registers word address register name description reset value ? 0x0800 egcr[15:0] emif global control register xxxx xxxx 0010 xx00 0x0801 emi_rst emif global reset register xxxx xxxx xxxx xxxx 0x0802 emi_be[13:0] emif bus error status register xx00 0000 0000 0000 0x0803 ce0_1[14:0] emif ce0 space control register 1 x010 1111 1111 1111 0x0804 ce0_2[15:0] emif ce0 space control register 2 0100 1111 1111 1111 0x0805 ce0_3[7:0] emif ce0 space control register 3 xxxx xxxx 0000 0000 0x0806 ce1_1[14:0] emif ce1 space control register 1 x010 1111 1111 1111 0x0807 ce1_2[15:0] emif ce1 space control register 2 0100 1111 1111 1111 0x0808 ce1_3[7:0] emif ce1 space control register 3 xxxx xxxx 0000 0000 0x0809 ce2_1[14:0] emif ce2 space control register 1 x010 1111 1111 1111 0x080a ce2_2[15:0] emif ce2 space control register 2 0101 1111 1111 1111 0x080b ce2_3[7:0] emif ce2 space control register 3 xxxx xxxx 0000 0000 0x080c ce3_1[14:0] emif ce3 space control register 1 x010 1111 1111 1111 0x080d ce3_2[15:0] emif ce3 space control register 2 0101 1111 1111 1111 0x080e ce3_3[7:0] emif ce3 space control register 3 xxxx xxxx 0000 0000 0x080f sdc1[15:0] emif sdram control register 1 1111 1001 0100 1000 0x0810 sdper[11:0] emif sdram period register xxxx 0000 1000 0000 0x0811 sdcnt[11:0] emif sdram counter register xxxx 0000 1000 0000 0x0812 init emif sdram init register xxxx xxxx xxxx xxxx 0x0813 sdc2[9:0] emif sdram control register 2 xxxx xx11 1111 1111 0x0814 sdc3 emif sdram control register 3 0000 0000 0000 0111 ? hardware reset; x denotes a ?don?t care.?
functional overview 49 april 2004 ? revised january 2008 sprs245j table 3?18. dma configuration registers port address (word) register name description reset value ? global register 0x0e00 dma_gcr[2:0] dma global control register xxxx xxxx xxxx x000 0x0e02 dma_gscr dma software compatibility register 0x0e03 dma_gtcr dma timeout control register channel #0 registers 0x0c00 dma_csdp0 dma channel 0 source destination parameters register 0000 0000 0000 0000 0x0c01 dma_ccr0[15:0] dma channel 0 control register 0000 0000 0000 0000 0x0c02 dma_cicr0[5:0] dma channel 0 interrupt control register xxxx xxxx xx00 0011 0x0c03 dma_csr0[6:0] dma channel 0 status register xxxx xxxx xx00 0000 0x0c04 dma_cssa_l0 dma channel 0 source start address register (lower bits) undefined 0x0c05 dma_cssa_u0 dma channel 0 source start address register (upper bits) undefined 0x0c06 dma_cdsa_l0 dma channel 0 source destination address register (lower bits) undefined 0x0c07 dma_cdsa_u0 dma channel 0 source destination address register (upper bits) undefined 0x0c08 dma_cen0 dma channel 0 element number register undefined 0x0c09 dma_cfn0 dma channel 0 frame number register undefined 0x0c0a dma_csfi0 dma channel 0 source frame index register undefined 0x0c0b dma_csei0 dma channel 0 source element index register undefined 0x0c0c dma_csac0 dma channel 0 source address counter undefined 0x0c0d dma_cdac0 dma channel 0 destination address counter undefined 0x0c0e dma_cdei0 dma channel 0 destination element index register undefined 0x0c0f dma_cdfi0 dma channel 0 destination frame index register undefined ? hardware reset: x denotes a ?don?t care.?
functional overview 50 april 2004 ? revised january 2008 sprs245j table 3?18. dma configuration registers (continued) port address (word) reset value ? description register name channel #1 registers 0x0c20 dma_csdp1 dma channel 1 source destination parameters register 0000 0000 0000 0000 0x0c21 dma_ccr1[15:0] dma channel 1 control register 0000 0000 0000 0000 0x0c22 dma_cicr1[5:0] dma channel 1 interrupt control register xxxx xxxx xx00 0011 0x0c23 dma_csr1[6:0] dma channel 1 status register xxxx xxxx xx00 0000 0x0c24 dma_cssa_l1 dma channel 1 source start address register (lower bits) undefined 0x0c25 dma_cssa_u1 dma channel 1 source start address register (upper bits) undefined 0x0c26 dma_cdsa_l1 dma channel 1 source destination address register (lower bits) undefined 0x0c27 dma_cdsa_u1 dma channel 1 source destination address register (upper bits) undefined 0x0c28 dma_cen1 dma channel 1 element number register undefined 0x0c29 dma_cfn1 dma channel 1 frame number register undefined 0x0c2a dma_csfi1 dma channel 1 source frame index register undefined 0x0c2b dma_csei1 dma channel 1 source element index register undefined 0x0c2c dma_csac1 dma channel 1 source address counter undefined 0x0c2d dma_cdac1 dma channel 1 destination address counter undefined 0x0c2e dma_cdei1 dma channel 1 destination element index register undefined 0x0c2f dma_cdfi1 dma channel 1 destination frame index register undefined channel #2 registers 0x0c40 dma_csdp2 dma channel 2 source destination parameters register 0000 0000 0000 0000 0x0c41 dma_ccr2[15:0] dma channel 2 control register 0000 0000 0000 0000 0x0c42 dma_cicr2[5:0] dma channel 2 interrupt control register xxxx xxxx xx00 0011 0x0c43 dma_csr2[6:0] dma channel 2 status register xxxx xxxx xx00 0000 0x0c44 dma_cssa_l2 dma channel 2 source start address register (lower bits) undefined 0x0c45 dma_cssa_u2 dma channel 2 source start address register (upper bits) undefined 0x0c46 dma_cdsa_l2 dma channel 2 source destination address register (lower bits) undefined 0x0c47 dma_cdsa_u2 dma channel 2 source destination address register (upper bits) undefined 0x0c48 dma_cen2 dma channel 2 element number register undefined 0x0c49 dma_cfn2 dma channel 2 frame number register undefined 0x0c4a dma_csfi2 dma channel 2 source frame index register undefined 0x0c4b dma_csei2 dma channel 2 source element index register undefined 0x0c4c dma_csac2 dma channel 2 source address counter undefined 0x0c4d dma_cdac2 dma channel 2 destination address counter undefined 0x0c4e dma_cdei2 dma channel 2 destination element index register undefined 0x0c4f dma_cdfi2 dma channel 2 destination frame index register undefined ? hardware reset: x denotes a ?don?t care.?
functional overview 51 april 2004 ? revised january 2008 sprs245j table 3?18. dma configuration registers (continued) port address (word) reset value ? description register name channel #3 registers 0x0c60 dma_csdp3 dma channel 3 source destination parameters register 0000 0000 0000 0000 0x0c61 dma_ccr3[15:0] dma channel 3 control register 0000 0000 0000 0000 0x0c62 dma_cicr3[5:0] dma channel 3 interrupt control register xxxx xxxx xx00 0011 0x0c63 dma_csr3[6:0] dma channel 3 status register xxxx xxxx xx00 0000 0x0c64 dma_cssa_l3 dma channel 3 source start address register (lower bits) undefined 0x0c65 dma_cssa_u3 dma channel 3 source start address register (upper bits) undefined 0x0c66 dma_cdsa_l3 dma channel 3 source destination address register (lower bits) undefined 0x0c67 dma_cdsa_u3 dma channel 3 source destination address register (upper bits) undefined 0x0c68 dma_cen3 dma channel 3 element number register undefined 0x0c69 dma_cfn3 dma channel 3 frame number register undefined 0x0c6a dma_csfi3 dma channel 3 source frame index register undefined 0x0c6b dma_csei3 dma channel 3 source element index register undefined 0x0c6c dma_csac3 dma channel 3 source address counter undefined 0x0c6d dma_cdac3 dma channel 3 destination address counter undefined 0x0c6e dma_cdei3 dma channel 3 destination element index register undefined 0x0c6f dma_cdfi3 dma channel 3 destination frame index register undefined channel #4 registers 0x0c80 dma_csdp4 dma channel 4 source destination parameters register 0000 0000 0000 0000 0x0c81 dma_ccr4[15:0] dma channel 4 control register 0000 0000 0000 0000 0x0c82 dma_cicr4[5:0] dma channel 4 interrupt control register xxxx xxxx xx00 0011 0x0c83 dma_csr4[6:0] dma channel 4 status register xxxx xxxx xx00 0000 0x0c84 dma_cssa_l4 dma channel 4 source start address register (lower bits) undefined 0x0c85 dma_cssa_u4 dma channel 4 source start address register (upper bits) undefined 0x0c86 dma_cdsa_l4 dma channel 4 source destination address register (lower bits) undefined 0x0c87 dma_cdsa_u4 dma channel 4 source destination address register (upper bits) undefined 0x0c88 dma_cen4 dma channel 4 element number register undefined 0x0c89 dma_cfn4 dma channel 4 frame number register undefined 0x0c8a dma_csfi4 dma channel 4 source frame index register undefined 0x0c8b dma_csei4 dma channel 4 source element index register undefined 0x0c8c dma_csac4 dma channel 4 source address counter undefined 0x0c8d dma_cdac4 dma channel 4 destination address counter undefined 0x0c8e dma_cdei4 dma channel 4 destination element index register undefined 0x0c8f dma_cdfi4 dma channel 4 destination frame index register undefined ? hardware reset: x denotes a ?don?t care.?
functional overview 52 april 2004 ? revised january 2008 sprs245j table 3?18. dma configuration registers (continued) port address (word) reset value ? description register name channel #5 registers 0x0ca0 dma_csdp5 dma channel 5 source destination parameters register 0000 0000 0000 0000 0x0ca1 dma_ccr5[15:0] dma channel 5 control register 0000 0000 0000 0000 0x0ca2 dma_cicr5[5:0] dma channel 5 interrupt control register xxxx xxxx xx00 0011 0x0ca3 dma_csr5[6:0] dma channel 5 status register xxxx xxxx xx00 0000 0x0ca4 dma_cssa_l5 dma channel 5 source start address register (lower bits) undefined 0x0ca5 dma_cssa_u5 dma channel 5 source start address register (upper bits) undefined 0x0ca6 dma_cdsa_l5 dma channel 5 source destination address register (lower bits) undefined 0x0ca7 dma_cdsa_u5 dma channel 5 source destination address register (upper bits) undefined 0x0ca8 dma_cen5 dma channel 5 element number register undefined 0x0ca9 dma_cfn5 dma channel 5 frame number register undefined 0x0caa dma_csfi5 dma channel 5 source frame index register undefined 0x0cab dma_csei5 dma channel 5 source element index register undefined 0x0cac dma_csac5 dma channel 5 source address counter undefined 0x0cad dma_cdac5 dma channel 5 destination address counter undefined 0x0cae dma_cdei5 dma channel 5 destination element index register undefined 0x0caf dma_cdfi5 dma channel 5 destination frame index register undefined ? hardware reset: x denotes a ?don?t care.? table 3?19. real-time clock registers word address register name description reset value ? 0x1800 rtcsec seconds register 0000 0000 0000 0000 0x1801 rtcseca seconds alarm register 0000 0000 0000 0000 0x1802 rtcmin minutes register 0000 0000 0000 0000 0x1803 rtcmina minutes alarm register 0000 0000 0000 0000 0x1804 rtchour hours register 0000 0000 0000 0000 0x1805 rtchoura hours alarm register 0000 0000 0000 0000 0x1806 rtcdayw day of the week register 0000 0000 0000 0000 0x1807 rtcdaym day of the month (date) register 0000 0000 0000 0000 0x1808 rtcmonth month register 0000 0000 0000 0000 0x1809 rtcyear year register 0000 0000 0000 0000 0x180a rtcpintr periodic interrupt selection register 0000 0000 0000 0000 0x180b rtcinten interrupt enable register 0000 0000 1000 0000 0x180c rtcintfl interrupt flag register 0000 0000 0000 0000 0x180d?0x1bff reserved ? hardware reset; x denotes a ?don?t care.?
functional overview 53 april 2004 ? revised january 2008 sprs245j table 3?20. clock generator word address register name description reset value ? 0x1c00 clkmd[14:0] clock mode register 0010 0000 0000 0010 div1 mode ? hardware reset; x denotes a ?don?t care.? table 3?21. timers word address register name description reset value ? 0x1000 tim0[15:0] timer count register, timer #0 1111 1111 1111 1111 0x1001 prd0[15:0] period register, timer #0 1111 1111 1111 1111 0x1002 tcr0[15:0] timer control register, timer #0 0000 0000 0001 0000 0x1003 prsc0[15:0] timer prescaler register, timer #0 xxxx 0000 xxxx 0000 0x2400 tim1[15:0] timer count register, timer #1 1111 1111 1111 1111 0x2401 prd1[15:0] period register, timer #1 1111 1111 1111 1111 0x2402 tcr1[15:0] timer control register, timer #1 0000 0000 0001 0000 0x2403 prsc1[15:0] timer prescaler register, timer #1 xxxx 0000 xxxx 0000 ? hardware reset; x denotes a ?don?t care.?
functional overview 54 april 2004 ? revised january 2008 sprs245j table 3?22. multichannel serial port #0 port address (word) register name description reset value ? 0x2800 drr2_0[15:0] data receive register 2, mcbsp #0 0000 0000 0000 0000 0x2801 drr1_0[15:0] data receive register 1, mcbsp #0 0000 0000 0000 0000 0x2802 dxr2_0[15:0] data transmit register 2, mcbsp #0 0000 0000 0000 0000 0x2803 dxr1_0[15:0] data transmit register 1, mcbsp #0 0000 0000 0000 0000 0x2804 spcr2_0[15:0] serial port control register 2, mcbsp #0 0000 0000 0000 0000 0x2805 spcr1_0[15:0] serial port control register 1, mcbsp #0 0000 0000 0000 0000 0x2806 rcr2_0[15:0] receive control register 2, mcbsp #0 0000 0000 0000 0000 0x2807 rcr1_0[15:0] receive control register 1, mcbsp #0 0000 0000 0000 0000 0x2808 xcr2_0[15:0] transmit control register 2, mcbsp #0 0000 0000 0000 0000 0x2809 xcr1_0[15:0] transmit control register 1, mcbsp #0 0000 0000 0000 0000 0x280a srgr2_0[15:0] sample rate generator register 2, mcbsp #0 0020 0000 0000 0000 0x280b srgr1_0[15:0] sample rate generator register 1, mcbsp #0 0000 0000 0000 0001 0x280c mcr2_0[15:0] multichannel control register 2, mcbsp #0 0000 0000 0000 0000 0x280d mcr1_0[15:0] multichannel control register 1, mcbsp #0 0000 0000 0000 0000 0x280e rcera_0[15:0] receive channel enable register partition a, mcbsp #0 0000 0000 0000 0000 0x280f rcerb_0[15:0] receive channel enable register partition b, mcbsp #0 0000 0000 0000 0000 0x2810 xcera_0[15:0] transmit channel enable register partition a, mcbsp #0 0000 0000 0000 0000 0x2811 xcerb_0[15:0] transmit channel enable register partition b, mcbsp #0 0000 0000 0000 0000 0x2812 pcr0[15:0] pin control register, mcbsp #0 0000 0000 0000 0000 0x2813 rcerc_0[15:0] receive channel enable register partition c, mcbsp #0 0000 0000 0000 0000 0x2814 rcerd_0[15:0] receive channel enable register partition d, mcbsp #0 0000 0000 0000 0000 0x2815 xcerc_0[15:0] transmit channel enable register partition c, mcbsp #0 0000 0000 0000 0000 0x2816 xcerd_0[15:0] transmit channel enable register partition d, mcbsp #0 0000 0000 0000 0000 0x2817 rcere_0[15:0] receive channel enable register partition e, mcbsp #0 0000 0000 0000 0000 0x2818 rcerf_0[15:0] receive channel enable register partition f, mcbsp #0 0000 0000 0000 0000 0x2819 xcere_0[15:0] transmit channel enable register partition e, mcbsp #0 0000 0000 0000 0000 0x281a xcerf_0[15:0] transmit channel enable register partition f, mcbsp #0 0000 0000 0000 0000 0x281b rcerg_0[15:0] receive channel enable register partition g, mcbsp #0 0000 0000 0000 0000 0x281c rcerh_0[15:0] receive channel enable register partition h, mcbsp #0 0000 0000 0000 0000 0x281d xcerg_0[15:0] transmit channel enable register partition g, mcbsp #0 0000 0000 0000 0000 0x281e xcerh_0[15:0] transmit channel enable register partition h, mcbsp #0 0000 0000 0000 0000 ? hardware reset; x denotes a ?don?t care.?
functional overview 55 april 2004 ? revised january 2008 sprs245j table 3?23. multichannel serial port #1 port address (word) register name description reset value ? 0x2c00 drr2_1[15:0] data receive register 2, mcbsp #1 0000 0000 0000 0000 0x2c01 drr1_1[15:0] data receive register 1, mcbsp #1 0000 0000 0000 0000 0x2c02 dxr2_1[15:0] data transmit register 2, mcbsp #1 0000 0000 0000 0000 0x2c03 dxr1_1[15:0] data transmit register 1, mcbsp #1 0000 0000 0000 0000 0x2c04 spcr2_1[15:0] serial port control register 2, mcbsp #1 0000 0000 0000 0000 0x2c05 spcr1_1[15:0] serial port control register 1, mcbsp #1 0000 0000 0000 0000 0x2c06 rcr2_1[15:0] receive control register 2, mcbsp #1 0000 0000 0000 0000 0x2c07 rcr1_1[15:0] receive control register 1, mcbsp #1 0000 0000 0000 0000 0x2c08 xcr2_1[15:0] transmit control register 2, mcbsp #1 0000 0000 0000 0000 0x2c09 xcr1_1[15:0] transmit control register 1, mcbsp #1 0000 0000 0000 0000 0x2c0a srgr2_1[15:0] sample rate generator register 2, mcbsp #1 0020 0000 0000 0000 0x2c0b srgr1_1[15:0] sample rate generator register 1, mcbsp #1 0000 0000 0000 0001 0x2c0c mcr2_1[15:0] multichannel control register 2, mcbsp #1 0000 0000 0000 0000 0x2c0d mcr1_1[15:0] multichannel control register 1, mcbsp #1 0000 0000 0000 0000 0x2c0e rcera_1[15:0] receive channel enable register partition a, mcbsp #1 0000 0000 0000 0000 0x2c0f rcerb_1[15:0] receive channel enable register partition b, mcbsp #1 0000 0000 0000 0000 0x2c10 xcera_1[15:0] transmit channel enable register partition a, mcbsp #1 0000 0000 0000 0000 0x2c11 xcerb_1[15:0] transmit channel enable register partition b, mcbsp #1 0000 0000 0000 0000 0x2c12 pcr1[15:0] pin control register, mcbsp #1 0000 0000 0000 0000 0x2c13 rcerc_1[15:0] receive channel enable register partition c, mcbsp #1 0000 0000 0000 0000 0x2c14 rcerd_1[15:0] receive channel enable register partition d, mcbsp #1 0000 0000 0000 0000 0x2c15 xcerc_1[15:0] transmit channel enable register partition c, mcbsp #1 0000 0000 0000 0000 0x2c16 xcerd_1[15:0] transmit channel enable register partition d, mcbsp #1 0000 0000 0000 0000 0x2c17 rcere_1[15:0] receive channel enable register partition e, mcbsp #1 0000 0000 0000 0000 0x2c18 rcerf_1[15:0] receive channel enable register partition f, mcbsp #1 0000 0000 0000 0000 0x2c19 xcere_1[15:0] transmit channel enable register partition e, mcbsp #1 0000 0000 0000 0000 0x2c1a xcerf_1[15:0] transmit channel enable register partition f, mcbsp #1 0000 0000 0000 0000 0x2c1b rcerg_1[15:0] receive channel enable register partition g, mcbsp #1 0000 0000 0000 0000 0x2c1c rcerh_1[15:0] receive channel enable register partition h, mcbsp #1 0000 0000 0000 0000 0x2c1d xcerg_1[15:0] transmit channel enable register partition g, mcbsp #1 0000 0000 0000 0000 0x2c1e xcerh_1[15:0] transmit channel enable register partition h, mcbsp #1 0000 0000 0000 0000 ? hardware reset; x denotes a ?don?t care.?
functional overview 56 april 2004 ? revised january 2008 sprs245j table 3?24. multichannel serial port #2 port address (word) register name description reset value ? 0x3000 drr2_2[15:0] data receive register 2, mcbsp #2 0000 0000 0000 0000 0x3001 drr1_2[15:0] data receive register 1, mcbsp #2 0000 0000 0000 0000 0x3002 dxr2_2[15:0] data transmit register 2, mcbsp #2 0000 0000 0000 0000 0x3003 dxr1_2[15:0] data transmit register 1, mcbsp #2 0000 0000 0000 0000 0x3004 spcr2_2[15:0] serial port control register 2, mcbsp #2 0000 0000 0000 0000 0x3005 spcr1_2[15:0] serial port control register 1, mcbsp #2 0000 0000 0000 0000 0x3006 rcr2_2[15:0] receive control register 2, mcbsp #2 0000 0000 0000 0000 0x3007 rcr1_2[15:0] receive control register 1, mcbsp #2 0000 0000 0000 0000 0x3008 xcr2_2[15:0] transmit control register 2, mcbsp #2 0000 0000 0000 0000 0x3009 xcr1_2[15:0] transmit control register 1, mcbsp #2 0000 0000 0000 0000 0x300a srgr2_2[15:0] sample rate generator register 2, mcbsp #2 0020 0000 0000 0000 0x300b srgr1_2[15:0] sample rate generator register 1, mcbsp #2 0000 0000 0000 0001 0x300c mcr2_2[15:0] multichannel control register 2, mcbsp #2 0000 0000 0000 0000 0x300d mcr1_2[15:0] multichannel control register 1, mcbsp #2 0000 0000 0000 0000 0x300e rcera_2[15:0] receive channel enable register partition a, mcbsp #2 0000 0000 0000 0000 0x300f rcerb_2[15:0] receive channel enable register partition b, mcbsp #2 0000 0000 0000 0000 0x3010 xcera_2[15:0] transmit channel enable register partition a, mcbsp #2 0000 0000 0000 0000 0x3011 xcerb_2[15:0] transmit channel enable register partition b, mcbsp #2 0000 0000 0000 0000 0x3012 pcr2[15:0] pin control register, mcbsp #2 0000 0000 0000 0000 0x3013 rcerc_2[15:0] receive channel enable register partition c, mcbsp #2 0000 0000 0000 0000 0x3014 rcerd_2[15:0] receive channel enable register partition d, mcbsp #2 0000 0000 0000 0000 0x3015 xcerc_2[15:0] transmit channel enable register partition c, mcbsp #2 0000 0000 0000 0000 0x3016 xcerd_2[15:0] transmit channel enable register partition d, mcbsp #2 0000 0000 0000 0000 0x3017 rcere_2[15:0] receive channel enable register partition e, mcbsp #2 0000 0000 0000 0000 0x3018 rcerf_2[15:0] receive channel enable register partition f, mcbsp #2 0000 0000 0000 0000 0x3019 xcere_2[15:0] transmit channel enable register partition e, mcbsp #2 0000 0000 0000 0000 0x301a xcerf_2[15:0] transmit channel enable register partition f, mcbsp #2 0000 0000 0000 0000 0x301b rcerg_2[15:0] receive channel enable register partition g, mcbsp #2 0000 0000 0000 0000 0x301c rcerh_2[15:0] receive channel enable register partition h, mcbsp #2 0000 0000 0000 0000 0x301d xcerg_2[15:0] transmit channel enable register partition g, mcbsp #2 0000 0000 0000 0000 0x301e xcerh_2[15:0] transmit channel enable register partition h, mcbsp #2 0000 0000 0000 0000 ? hardware reset; x denotes a ?don?t care.?
functional overview 57 april 2004 ? revised january 2008 sprs245j table 3?25. gpio word address register name pin description reset value ? 0x3400 iodir[7:0] gpio[7:0] general-purpose i/o direction register 0000 0000 0000 0000 0x3401 iodata[7:0] gpio[7:0] general-purpose i/o data register 0000 0000 xxxx xxxx 0x4400 agpioen[15:0] a[15:0] address/gpio enable register 0000 0000 0000 0000 0x4401 agpiodir[15:0] a[15:0] address/gpio direction register 0000 0000 0000 0000 0x4402 agpiodata[15:0] a[15:0] address/gpio data register xxxx xxxx xxxx xxxx 0x4403 ehpigpioen[5:0] gpio[13:8] ehpi/gpio enable register 0000 0000 0000 0000 0x4404 ehpigpiodir[5:0] gpio[13:8] ehpi/gpio direction register 0000 0000 0000 0000 0x4405 ehpigpiodata[5:0] gpio[13:8] ehpi/gpio data register 0000 0000 00xx xxxx ? hardware reset; x denotes a ?don?t care.? table 3?26. device revision id word address register name description value ? 0x3803 rev id[4:1] silicon revision identification rev. 1.0: xxxx xxxx xxx0 001x ? x denotes a ?don?t care.? table 3?27. i 2 c module registers word address register name description reset value ? 0x3c00 i2coar[9:0] i 2 c own address register 0000 0000 0000 0000 0x3c01 i2cier i 2 c interrupt enable register 0000 0000 0000 0000 0x3c02 i2cstr i 2 c status register 0000 0001 0000 0000 0x3c03 i2cclkl[15:0] i 2 c clock divider low register 0000 0000 0000 0000 0x3c04 i2cclkh[15:0] i 2 c clock divider high register 0000 0000 0000 0000 0x3c05 i2ccnt[15:0] i 2 c data count 0000 0000 0000 0000 0x3c06 i2cdrr[7:0] i 2 c data receive register 0000 0000 0000 0000 0x3c07 i2csar[9:0] i 2 c slave address register 0000 0011 1111 1111 0x3c08 i2cdxr[7:0] i 2 c data transmit register 0000 0000 0000 0000 0x3c09 i2cmdr[14:0] i 2 c mode register 0000 0000 0000 0000 0x3c0a i2cisrc i 2 c interrupt source register 0000 0000 0000 0000 0x3c0b ? reserved 0x3c0c i2cpsc i 2 c prescaler register 0000 0000 0000 0000 0x3c0d ? reserved 0x3c0e ? reserved 0x3c0f i2cmdr2 i 2 c mode register 2 0000 0000 0000 0000 ? i2crsr i 2 c receive shift register (not accessible to the cpu) ? i2cxsr i 2 c transmit shift register (not accessible to the cpu) ? hardware reset; x denotes a ?don?t care.? this register must be set by the user. the user may program the i 2 c?s own address to any value, as long as the value does not conflict with the i 2 c addresses of other components connected to the i 2 c bus. note: i 2 c protocol compatible, no fail-safe buffer.
functional overview 58 april 2004 ? revised january 2008 sprs245j table 3?28. watchdog timer registers word address register name description reset value ? 0x4000 wdtim[15:0] wd timer counter register 1111 1111 1111 1111 0x4001 wdprd[15:0] wd timer period register 1111 1111 1111 1111 0x4002 wdtcr[13:0] wd timer control register 0000 0011 1100 1111 0x4003 wdtcr2[15:0] wd timer control register 2 0001 0000 0000 0000 ? hardware reset; x denotes a ?don?t care.? table 3?29. external bus selection register word address register name description reset value ? 0x6c00 ebsr[15:0] external bus selection register 0000 0000 0000 0011 ? ? hardware reset; x denotes a ?don?t care.? ? the reset value is 0000 0000 0000 0001 if gpio0 = 1; the value is 0000 0000 0000 0011 if gpio0 = 0.
functional overview 59 april 2004 ? revised january 2008 sprs245j 3.10 interrupts vector-relative locations and priorities for all internal and external interrupts are shown in table 3?30. table 3?30. interrupt table name software (trap) equivalent relative location ? (hex bytes) priority function reset sint0 0 0 reset (hardware and software) nmi ? sint1 8 1 nonmaskable interrupt berr sint24 c0 2 bus error interrupt int0 sint2 10 3 external interrupt #0 int1 sint16 80 4 external interrupt #1 int2 sint3 18 5 external interrupt #2 tint0 sint4 20 6 timer #0 interrupt rint0 sint5 28 7 mcbsp #0 receive interrupt xint0 sint17 88 8 mcbsp #0 transmit interrupt rint1 sint6 30 9 mcbsp #1 receive interrupt xint1 sint7 38 10 mcbsp #1 transmit interrupt ? sint8 40 11 software interrupt #8 dmac0 sint18 90 12 dma channel #0 interrupt dmac1 sint9 48 13 dma channel #1 interrupt dspint sint10 50 14 interrupt from host int3/wdtint sint11 58 15 external interrupt #3 or watchdog timer interrupt int4/rtc sint19 98 16 external interrupt #4 or rtc interrupt rint2 sint12 60 17 mcbsp #2 receive interrupt xint2 sint13 68 18 mcbsp #2 transmit interrupt dmac2 sint20 a0 19 dma channel #2 interrupt dmac3 sint21 a8 20 dma channel #3 interrupt dmac4 sint14 70 21 dma channel #4 interrupt dmac5 sint15 78 22 dma channel #5 interrupt tint1 sint22 b0 23 timer #1 interrupt iic sint23 b8 24 i 2 c interrupt dlog sint25 c8 25 data log interrupt rtos sint26 d0 26 real-time operating system interrupt ? sint27 d8 27 software interrupt #27 ? sint28 e0 28 software interrupt #28 ? sint29 e8 29 software interrupt #29 ? sint30 f0 30 software interrupt #30 ? sint31 f8 31 software interrupt #31 ? absolute addresses of the interrupt vector locations are determined by the contents of the ivpd and ivph registers. interrupt v ectors for interrupts 0?15 and 24?31 are relative to ivpd. interrupt vectors for interrupts 16?23 are relative to ivph. ? the nmi pin is internally tied high. however, nmi interrupt vector can be used for sint1 and watchdog timer interrupt. it is recommended that either the int4 or rtc interrupt be used. if both int4 and rtc interrupts are used, one interrupt event can potentially hold off the other interrupt. for example, if int4 is asserted first and held low, the rtc interrupt will not be recognized until the int4 pin is back to high-logic state again. the int4 pin must be pulled high if only the rtc interrupt is used.
functional overview 60 april 2004 ? revised january 2008 sprs245j 3.10.1 ifr and ier registers the ifr0 (interrupt flag register 0) and ier0 (interrupt enable register 0) bit layouts are shown in figure 3?17. 15 14 13 12 11 10 9 8 dmac5 dmac4 xint2 rint2 int3/ wdtint dspint dmac1 reserved r/w r/w r/w r/w r/w r/w r/w 76543210 xint1 rint1 rint0 tint0 int2 int0 reserved r/w r/w r/w r/w r/w r/w legend: r = read, w = write, n = value after reset figure 3?17. ifr0 and ier0 bit locations table 3?31. ifr0 and ier0 register bit fields bit function number name function 15 dmac5 dma channel 5 interrupt flag/mask bit 14 dmac4 dma channel 4 interrupt flag/mask bit 13 xint2 this bit is used as the mcbsp2 transmit interrupt flag/mask bit. 12 rint2 mcbsp2 receive interrupt flag/mask bit. 11 int3/wdtint this bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt flag/mask bit. ? 10 dspint hpi host-to-dsp interrupt flag/mask. 9 dmac1 dma channel 1 interrupt flag/mask bit 8 ? reserved. this bit should always be written with 0. 7 xint1 this bit is used as the mcbsp1 transmit interrupt flag/mask bit. 6 rint1 mcbsp1 receive interrupt flag/mask bit. 5 rint0 mcbsp0 receive interrupt flag bit 4 tint0 timer 0 interrupt flag bit 3 int2 external interrupt 2 flag bit 2 int0 external interrupt 0 flag bit 1?0 ? reserved for future expansion. these bits should always be written with 0. ? it is possible to have active interrupts simultaneously from both the external int3 source and the watchdog timer. when an inte rrupt is detected in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source.
functional overview 61 april 2004 ? revised january 2008 sprs245j the ifr1 (interrupt flag register 1) and ier1 (interrupt enable register 1) bit layouts are shown in figure 3?18. note: it is possible to have active interrupts simultaneously from both the external interrupt 4 (int4) and the real-time clock (rtc). when an interrupt is detected in this bit, the real-time clock status register should be polled to determine if the real-time clock is the source of the interrupt. 15 11 10 9 8 reserved rtos dlog berr r/w?00000 ? r/w?0 r/w?0 r/w?0 76543210 i2c tint1 dmac3 dmac2 int4/rtc dmac0 xint0 int1 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 r/w?0 legend: r = read, w = write, n = value after reset ? always write zeros. figure 3?18. ifr1 and ier1 bit locations table 3?32. ifr1 and ier1 register bit fields bit function number name function 15?11 ? reserved for future expansion. these bits should always be written with 0. 10 rtos real-time operating system interrupt flag/mask bit 9 dlog data log interrupt flag/mask bit 8 berr bus error interrupt flag/mask bit 7 i2c i2c interrupt flag/mask bit 6 tint1 timer 1 interrupt flag/mask bit 5 dmac3 dma channel 3 interrupt flag/mask bit 4 dmac2 dma channel 2 interrupt flag/mask bit 3 int4/rtc this bit can be used as either the external user interrupt 4 flag/mask bit, or the real-time clock interrupt flag/mask bit. 2 dmac0 dma channel 0 interrupt flag/mask bit 1 xint0 mcbsp transmit 0 interrupt flag/mask bit 0 int1 external user interrupt 1 flag/mask bit
functional overview 62 april 2004 ? revised january 2008 sprs245j 3.10.2 interrupt timing the external interrupts (int[4:0] ) are synchronized to the cpu by way of a two-flip-flop synchronizer. the interrupt inputs are sampled on falling edges of the cpu clock. a sequence of 1-1-0-0-0 on consecutive cycles on the interrupt pin is required for an interrupt to be detected. therefore, the minimum low pulse duration on the external interrupts on the 5503 is three cpu clock periods. 3.10.3 waking up from idle condition one of the following four events can wake up the cpu from idle: ? hardware reset ? external interrupt ? rtc interrupt 3.10.3.1 waking up from idle with oscillator disabled with an external interrupt or an r tc interrupt, the clock generation circuit wakes up the oscillator. in the case of the interrupt being disabled by clearing the associated bit in the interrupt enable register (ierx), the cpu is not ?woken up?. if the external interrupt serves as the wake-up event, the interrupt line must stay low for a minimum of 3 cpu cycles after the oscillator is stabilized to wake up the cpu. otherwise, only the clock domain will wake up and another external interrupt will be needed to wake up the cpu. 3.10.4 idling clock domain when external parallel bus operating in ehpi mode the clock domain cannot be idled when the external parallel bus is operating in ehpi mode to ensure host access to the dsp memory. to work around this restriction, use the hidl bit of the external bus selection register (ebsr) with the clkgeni bit of the idle control register (icr) to idle the clock domain.
support 63 april 2004 ? revised january 2008 sprs245j 4 support 4.1 notices concerning jtag (ieee 1149.1) boundary scan test capability 4.1.1 initialization requirements for boundary scan test the tms320vc5503 uses the jtag port for boundary scan tests, emulation capability and factory test purposes. to use boundary scan test, the emu0 and emu1/off pins must be held low through a rising edge of the trst signal prior to the first scan. this operation selects the appropriate tap control for boundary scan. if at any time during a boundary scan test a rising edge of trst occurs when emu0 or emu1/off are not low, a factory test mode may be selected preventing boundary scan test from being completed. for this reason, it is recommended that emu0 and emu1/off be pulled or driven low at all times during boundary scan test. 4.1.2 boundary scan description language (bsdl) model bsdl models are available on the web in the tms320vc5503 product folder under the ?simulation models? section. 4.2 documentation support extensive documentation supports all tms320 ? dsp family of devices from product announcement through applications development. the following types of documentation are available to support the design and use of the tms320c5000 ? platform of dsps: ? tms320c55x ? dsp functional overview (literature number spru312) ? device-specific data sheets and data manuals ? complete user?s guides ? development support tools ? hardware and software application reports tms320c55x reference documentation includes, but is not limited to, the following: ? tms320c55x dsp cpu reference guide (literature number spru371) ? tms320c55x dsp mnemonic instruction set reference guide (literature number spru374) ? tms320c55x dsp algebraic instruction set reference guide (literature number spru375) ? tms320c55x dsp programmer?s guide (literature number spru376) ? tms320c55x dsp peripherals overview reference guide (literature number spru317) ? tms320c55x optimizing c/c++ compiler user?s guide (literature number spru281) ? tms320c55x assembly language tools user?s guide (literature number spru280) ? tms320c55x dsp library programmer?s reference (literature number spru422) ? using the tms320vc5503/vc5507/vc5509/vc5509a bootloader application report (literature number spra375) the reference guides describe in detail the tms320c55x ? dsp products currently available and the hardware and software applications, including algorithms, for fixed-point tms320 ? dsp family of devices. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 ? dsp newsletter, details on signal processing , is published quarterly and distributed to update tms320 ? dsp customers on product information. information regardi ng ti dsp products is also available on the worldwide web at http://www.ti.com uniform resource locator (url). tms320 and tms320c5000 are trademarks of texas instruments.
support 64 april 2004 ? revised january 2008 sprs245j 4.3 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tms 320vc5503ghh). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx / tmdx) through fully qualified production devices/tools (tms / tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device? s electrical specifications tmp final silicon die that conforms to the device?s electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ?developmental product is intended for internal evaluation purposes.? tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, ghh). the zhh package, like the ghh package, is a 179-terminal plastic bga only with pb-free balls. for device part numbers and further ordering information for tms320vc5503 in the ghh and zhh package types, see the ti website (http://www.ti.com) or contact your ti sales representative.
support 65 april 2004 ? revised january 2008 sprs245j 4.4 tms320vc5503 device nomenclature prefix tms 320 vc 5503 ghh tmx = experimental device tmp = prototype device tms = qualified device smj = mil-std-883c sm = high rel (non-883c) device family 320 = tms320 family technology package type ? ? ghh = 179-terminal plastic bga zhh = 179-terminal plastic bga with pb-free soldered balls pge = 144-pin plastic lqfp vc = dual-supply cmos device 55x dsp: 5503 ? bga = ball grid array lqfp = low-profile quad flatpack ? the zhh mechanical package designator represents the version of the ghh with pb?free soldered balls. the zhh package devices are supported in the same speed grades as the ghh package devices ( available upon request ). for actual device part numbers (p/ns) and ordering information, see the mechanical data section of this document or the ti website (www.ti.com). figure 4?1. device nomenclature for the tms320vc5503
electrical specifications 66 april 2004 ? revised january 2008 sprs245j 5 electrical specifications this section provides the absolute maximum ratings and the recommended operating conditions for the tms320vc5503 dsp. all electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. 5.1 absolute maximum ratings the list of absolute maximum ratings are specified over operating case temperature. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under section 5.2 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to v ss . figure 5?1 provides the test load circuit values for a 3.3-v i/o. supply voltage i/o range, dv dd ? 0.3 v to 4.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage core range, cv dd ? 0.3 v to 2.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ? 0.3 v to 4.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.3 v to 4.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range t stg ? 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
electrical specifications 67 april 2004 ? revised january 2008 sprs245j 5.2 recommended operating conditions 5.2.1 recommended operating conditions for cv dd = 1.2 v (108 mhz) min nom max unit core cv dd device supply voltage 1.14 1.2 1.26 v peripherals rcv dd rtc module supply voltage, core 1.14 1.2 1.26 v rdv dd rtc module supply voltage, i/o (rtcinx1 and rtcinx2) 1.14 1.2 1.26 v dv dd device supply voltage, i/o (except sda and scl) ? 2.7 3.3 3.6 v grounds v ss supply voltage, gnd, i/o, and core 0 v v ih high-level input voltage, i/o sda & scl: v dd related input levels ? 0.7*dv dd dv dd (max) +0.5 v v ih high-level input voltage, i/o all other inputs (including hysteresis inputs) 2.0 dv dd + 0.3 v v il low-level input voltage, i/o sda &scl: v dd related input levels ? ?0.5 0.3 * dv dd v v il low-level input voltage, i/o all other inputs (including hysteresis inputs) ?0.3 0.8 v v hys hysteresis level inputs with hysteresis only 0.1*dv dd v i oh high-level output current all outputs ?4 ma i ol low-level output current sda and scl ? 3 ma i ol low-level output current all other outputs 4 ma t c operating case temperature ?40 85 c ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. due to the fact that different voltage devices can be connected to the i 2 c bus, the level of logic 0 (low) and logic 1 (high) are not fixed and depends on the associated v dd .
electrical specifications 68 april 2004 ? revised january 2008 sprs245j 5.2.2 recommended operating conditions for cv dd = 1.35 v (144 mhz) min nom max unit core cv dd device supply voltage 1.28 1.35 1.42 v peripherals rcv dd rtc module supply voltage, core 1.28 1.35 1.42 v rdv dd rtc module supply voltage, i/o (rtcinx1 and rtcinx2) 1.28 1.35 1.42 v dv dd device supply voltage, i/o (except sda and scl) ? 2.7 3.3 3.6 v grounds v ss supply voltage, gnd, i/o, and core 0 v v ih high-level input voltage, i/o sda & scl: v dd related input levels ? 0.7*dv dd dv dd (max) +0.5 v v ih high-level input voltage, i/o all other inputs (including hysteresis inputs) 2.0 dv dd + 0.3 v v il low-level input voltage, i/o sda &scl: v dd related input levels ? ?0.5 0.3 * dv dd v v il low-level input voltage, i/o all other inputs (including hysteresis inputs) ?0.3 0.8 v v hys hysteresis level inputs with hysteresis only 0.1*dv dd v i oh high-level output current all outputs ?4 ma i ol low-level output current sda and scl ? 3 ma i ol low-level output current all other outputs 4 ma t c operating case temperature ?40 85 c ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. due to the fact that different voltage devices can be connected to the i 2 c bus, the level of logic 0 (low) and logic 1 (high) are not fixed and depends on the associated v dd .
electrical specifications 69 april 2004 ? revised january 2008 sprs245j 5.2.3 recommended operating conditions for cv dd = 1.6 v (200 mhz) min nom max unit core cv dd device supply voltage 1.55 1.6 1.65 v peripherals rcv dd rtc module supply voltage, core 1.55 1.6 1.65 v rdv dd rtc module supply voltage, i/o (rtcinx1 and rtcinx2) 1.55 1.6 1.65 v dv dd device supply voltage, i/o (except sda and scl) ? 2.7 3.3 3.6 v grounds v ss supply voltage, gnd, i/o, and core 0 v v ih high-level input voltage, i/o sda & scl: v dd related input levels ? 0.7*dv dd dv dd (max) +0.5 v v ih high-level input voltage, i/o all other inputs (including hysteresis inputs) 2.0 dv dd + 0.3 v v il low-level input voltage, i/o sda & scl: v dd related input levels ? ?0.5 0.3 * dv dd v v il low-level input voltage, i/o all other inputs (including hysteresis inputs) ?0.3 0.8 v v hys hysteresis level inputs with hysteresis only 0.1*dv dd v i oh high-level output current all outputs ?4 ma i ol low-level output current sda and scl ? 3 ma i ol low-level output current all other outputs 4 ma t c operating case temperature ?40 85 c ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. due to the fact that different voltage devices can be connected to the i 2 c bus, the level of logic 0 (low) and logic 1 (high) are not fixed and depends on the associated v dd .
electrical specifications 70 april 2004 ? revised january 2008 sprs245j 5.3 electrical characteristics 5.3.1 electrical characteristics over recommended operating case temperature range for cv dd = 1.2 v (108 mhz) (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage all outputs dv dd = 2.7 v?3.6 v, i oh = max 0.75 * dv dd v v ol low-level output voltage sda & scl ? at 3 ma sink current 0 0.4 v v ol low-level output voltage all other outputs i ol = max 0.4 v i iz input current for outputs in high-impedance output-only or i/o pins with bus keepers (enabled) dv dd = max, v o = v ss to dv dd ?300 300 a i iz input current for outputs in high-impedance all other output-only or i/o pins dv dd = max v o = v ss to dv dd ?5 5 a input pins with internal pulldown (enabled) dv dd = max, v i = v ss to dv dd 30 300 i i input current input pins with internal pullup (enabled) dv dd = max, v i = v ss to dv dd ?300 ?30 a i i input current x2/clkin dv dd = max, v i = v ss to dv dd ?50 50 a all other input-only pins dv dd = max, v i = v ss to dv dd ?5 5 i ddc cv dd supply current, cpu + internal memory access ? cv dd = 1.2 v cpu clock = 108 mhz t c = 25 c 0.45 ma/ mhz i ddp dv dd supply current, pins active dv dd = 3.3 v cpu clock = 108 mhz t c = 25 c 5.5 ma i ddc cv dd supply current, standby ? oscillator disabled. all domains in low-power state cv dd = 1.2 v t c = 25 c (nominal process) 100 a i ddp dv dd supply current, standby oscillator disabled. all domains in low-power state. dv dd = 3.3 v no i/o activity t c = 25 c 10 a c i input capacitance 3 pf c o output capacitance 3 pf ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. ? cpu executing 75% dual mac + 25% add with moderate data bus activity (table of sine values). cpu and clkgen (dpll) domain are a ctive. all other domains are idled. one word of a table of a 16-bit sine value is written to the emif every 250 ns (64 mbps). each emif output pin is connected to a 10-pf load. ? in clkgen domain idle mode, x2/clkin becomes output and is driven low to stop external crystals (if used) from oscillating. sta ndby current will be higher if an external clock source tries to drive the x2/clkin pin during this time.
electrical specifications 71 april 2004 ? revised january 2008 sprs245j 5.3.2 electrical characteristics over recommended operating case temperature range for cv dd = 1.35 v (144 mhz) (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage all outputs dv dd = 2.7 v?3.6 v, i oh = max 0.75 * dv dd v v ol low-level output voltage sda & scl ? at 3 ma sink current 0 0.4 v v ol low-level output voltage all other outputs i ol = max 0.4 v i iz input current for outputs in high-impedance output-only or i/o pins with bus keepers (enabled) dv dd = max, v o = v ss to dv dd ?300 300 a i iz input current for outputs in high-impedance all other output-only or i/o pins dv dd = max v o = v ss to dv dd ?5 5 a input pins with internal pulldown (enabled) dv dd = max, v i = v ss to dv dd 30 300 i i input current input pins with internal pullup (enabled) dv dd = max, v i = v ss to dv dd ?300 ?30 a i i input current x2/clkin dv dd = max, v i = v ss to dv dd ?50 50 a all other input-only pins dv dd = max, v i = v ss to dv dd ?5 5 i ddc cv dd supply current, cpu + internal memory access ? cv dd = 1.35 v cpu clock = 144 mhz t c = 25 c 0.51 ma/ mhz i ddp dv dd supply current, pins active dv dd = 3.3 v cpu clock = 144 mhz t c = 25 c 5.5 ma i ddc cv dd supply current, standby ? oscillator disabled. all domains in low-power state cv dd = 1.35 v t c = 25 c (nominal process) 125 a i ddp dv dd supply current, standby oscillator disabled. all domains in low-power state. dv dd = 3.3 v no i/o activity t c = 25 c 10 a c i input capacitance 3 pf c o output capacitance 3 pf ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. ? cpu executing 75% dual mac + 25% add with moderate data bus activity (table of sine values). cpu and clkgen (dpll) domain are a ctive. all other domains are idled. one word of a table of a 16-bit sine value is written to the emif every 250 ns (64 mbps). each emif output pin is connected to a 10-pf load. ? in clkgen domain idle mode, x2/clkin becomes output and is driven low to stop external crystals (if used) from oscillating. sta ndby current will be higher if an external clock source tries to drive the x2/clkin pin during this time.
electrical specifications 72 april 2004 ? revised january 2008 sprs245j 5.3.3 electrical characteristics over recommended operating case temperature range for cv dd = 1.6 v (200 mhz) (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage all outputs dv dd = 2.7 v?3.6 v, i oh = max 0.75 * dv dd v v ol low-level output voltage sda & scl ? at 3 ma sink current 0 0.4 v v ol low-level output voltage all other outputs i ol = max 0.4 v i iz input current for outputs in high-impedance output-only or i/o pins with bus keepers (enabled) dv dd = max, v o = v ss to dv dd ?300 300 a i iz input current for outputs in high-impedance all other output-only or i/o pins dv dd = max v o = v ss to dv dd ?5 5 a input pins with internal pulldown (enabled) dv dd = max, v i = v ss to dv dd 30 300 i i input current input pins with internal pullup (enabled) dv dd = max, v i = v ss to dv dd ?300 ?30 a i i input current x2/clkin dv dd = max, v i = v ss to dv dd ?50 50 a all other input-only pins dv dd = max, v i = v ss to dv dd ?5 5 i ddc cv dd supply current, cpu + internal memory access ? cv dd = 1.6 v cpu clock = 200 mhz t c = 25 c 0.60 ma/ mhz i ddp dv dd supply current, pins active dv dd = 3.3 v cpu clock = 200 mhz t c = 25 c 5.5 ma i ddc cv dd supply current, standby ? oscillator disabled. all domains in low-power state cv dd = 1.6 v t c = 25 c (nominal process) 150 a i ddp dv dd supply current, standby oscillator disabled. all domains in low-power state. dv dd = 3.3 v no i/o activity t c = 25 c 10 a c i input capacitance 3 pf c o output capacitance 3 pf ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. ? cpu executing 75% dual mac + 25% add with moderate data bus activity (table of sine values). cpu and clkgen (dpll) domain are a ctive. all other domains are idled. one word of a table of a 16-bit sine value is written to the emif every 250 ns (64 mbps). each emif output pin is connected to a 10-pf load. ? in clkgen domain idle mode, x2/clkin becomes output and is driven low to stop external crystals (if used) from oscillating. sta ndby current will be higher if an external clock source tries to drive the x2/clkin pin during this time.
electrical specifications 73 april 2004 ? revised january 2008 sprs245j transmission line 4.0 pf 1.85 pf z0 = 50 ? (see note) tester pin electronics data manual timing reference point output under test note: the data manual provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line eff ect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or l onger) from the data manual timings. 42 ? 3.5 nh device pin (see note) input requirements in this data manual are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin. figure 5?1. 3.3-v test load circuit 5.4 esd performance esd stress levels were performed in compliance with the following jedec standards with the results indicated below: ? charged device model (cdm), based on jedec specification jesd22-c101, passed at 500 v ? human body model (hbm), based on jedec specification jesd22-a114, passed at 1500 v note: according to industry research publications, esd-cdm testing results show better correlation to manufacturing line and field failure rates than esd-hbm testing. 500-v cdm is commonly considered as a safe passing level. 5.5 timing parameter symbology timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid dis disable time z high-impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) x unknown, changing, or don?t care level
electrical specifications 74 april 2004 ? revised january 2008 sprs245j 5.6 clock options the frequency of the reference clock provided at the x2/clkin pin can be divided by a factor of two or four or multiplied by one of several values to generate the internal machine cycle. 5.6.1 internal system oscillator with external crystal the internal oscillator is always enabled following a device reset. the oscillator requires an external crystal connected across the x1 and x2/clkin pins. if the internal oscillator is not used, an external clock source must be applied to the x2/clkin pin and the x1 pin should be left unconnected. since the internal oscillator can be used as a clock source to the plls, the crystal oscillation frequency can be multiplied to generate the cpu clock, if desired. the crystal should be in fundamental-mode operation, and parallel resonant, with a max imum effective series resistance (esr) specified in table 5?1. the connection of the required circuit is shown in figure 5?2. under some conditions, all the components shown are not required. the capacitors, c 1 and c 2 , should be chosen such that the equation below is satisfied. c l in the equation is the load specified for the crystal that is also specified in table 5?1. c l c 1 c 2 ( c 1 c 2 ) x2/clkin x1 c1 c2 crystal r s figure 5?2. internal system oscillator with external crystal table 5?1. recommended crystal parameters frequency range (mhz) max esr ( ? ) typ c load (pf) max c shunt (pf) r s ( ? ) 20?15 20 10 7 0 15?12 30 16 7 0 12?10 40 16 7 100 10?8 60 18 7 470 8?6 80 18 7 1.5k 6?5 80 18 7 2.2k although the recommended esr presented in table 5?1 is maximum, theoretically a crystal with a lower maximum esr might seem to meet the requirement. it is recommended that crystals which meet the maximum esr specification in table 5?1 are used.
electrical specifications 75 april 2004 ? revised january 2008 sprs245j 5.6.2 layout considerations since parasitic capacitance, inductance and resistance can be significant in any circuit, good pc board layout practices should always be observed when planning trace routing to the discrete components used in the oscillator circuit. specifically, the crystal and the associated discrete components should be located as close to the dsp as physically possible. also, x1 and x2/clkin traces should be separated as soon as possible after routing away from the dsp to minimize parasitic capacitance between them, and a ground trace should be run between these two signal lines. this also helps to minimize stray capacitance between these two signals.
electrical specifications 76 april 2004 ? revised january 2008 sprs245j 5.6.3 clock generation in bypass mode (dpll disabled) the frequency of the reference clock provided at the x2/clkin pin can be divided by a factor of one, two, or four to generate the internal cpu clock cycle. the divide factor (d) is set in the byp ass_div field of the clock mode register. the contents of this field only affect clock generation while the device is in bypass mode. in this mode, the digital phase-locked loop (dpll) clock synthesis is disabled. table 5?2 and table 5?3 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5?3). table 5?2. clkin timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit c1 t c(ci) cycle time, x2/clkin 20 400 ? 20 400 ? ns c2 t f(ci) fall time, x2/clkin 4 4 ns c3 t r(ci) rise time, x2/clkin 4 4 ns c10 t w(cil) pulse duration, clkin low 6 6 ns c11 t w(cih) pulse duration, clkin high 6 6 ns ? this device utilizes a fully static design and therefore can operate with t c(ci) approaching . if an external crystal is used, the x2/clkin cycle time is limited by the crystal frequency range listed in table 5?1. table 5?3. clkout switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min typ max min typ max unit c4 t c(co) cycle time, clkout 20 ? d*t c(ci) 1600 ? 20 ? d*t c(ci) 1600 ? ns c5 t d(ci-co) delay time, x2/clkin high to clkout high/low 5 15 25 5 15 25 ns c6 t f(co) fall time, clkout 1 1 ns c7 t r(co) rise time, clkout 1 1 ns c8 t w(col) pulse duration, clkout low h ? 1 h + 1 h ? 1 h + 1 ns c9 t w(coh) pulse duration, clkout high h ? 1 h + 1 h ? 1 h + 1 ns ? this device utilizes a fully static design and therefore can operate with t c(co) approaching . if an external crystal is used, the x2/clkin cycle time is limited by the crystal frequency range listed in table 5?1. ? it is recommended that the dpll synthesised clocking option be used to obtain maximum operating frequency. d = 1/(pll bypass divider) c3 c2 c1 c4 c5 c7 c6 c8 c9 x2/clkin clkout c10 c11 note a: the relationship of x2/clkin to clkout depends on the pll bypass divide factor chosen for the clkmd register. the wavefo rm relationship shown in figure 5?3 is intended to illustrate the timing parameters based on clkout = 1/2(clkin) configuration. figure 5?3. bypass mode clock timings
electrical specifications 77 april 2004 ? revised january 2008 sprs245j 5.6.4 clock generation in lock mode (dpll synthesis enabled) the frequency of the reference clock provided at the x2/clkin pin can be multiplied by a synthesis factor of n to generate the internal cpu clock cycle. the synthesis factor is determined by: n = m d l where: m = the multiply factor set in the pll_mult field of the clock mode register d l = the divide factor set in the pll_div field of the clock mode register valid values for m are (multiply by) 2 to 31. valid values for d l are (divide by) 1, 2, 3, and 4. for detailed information on clock generation configuration, see the tms320c55x dsp peripherals overview reference guide (literature number spru317). table 5?4 and table 5?5 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5?4). table 5?4. multiply-by-n clock option timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit c1 t c(ci) cycle time, x2/clkin dpll synthesis enabled 20 ? 400 20 ? 400 ns c2 t f(ci) fall time, x2/clkin 4 4 ns c3 t r(ci) rise time, x2/clkin 4 4 ns c10 t w(cil) pulse duration, clkin low 6 6 ns c11 t w(cih) pulse duration, clkin high 6 6 ns ? the clock frequency synthesis factor and minimum x2/clkin cycle time should be chosen such that the resulting clkout cycle time is within the specified range (t c(co) ). if an external crystal is used, the x2/clkin cycle time is limited by the crystal frequency range listed in table 5?1. table 5?5. multiply-by-n clock option switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min typ max min typ max min typ max unit c4 t c(co) cycle time, clkout 9.26 t c(ci)* n ? 1600 6.95 t c(ci)* n ? 1600 5 t c(ci)* n ? 1600 ns c6 t f(co) fall time, clkout 1 1 1 ns c7 t r(co) rise time, clkout 1 1 1 ns c8 t w(col) pulse duration, clkout low h ? 1 h + 1 h ? 1 h + 1 h ? 1 h + 1 ns c9 t w(coh) pulse duration, clkout high h ? 1 h + 1 h ? 1 h + 1 h ? 1 h + 1 ns c12 t d(ci?co) delay time, x2/clkin high/ low to clkout high/low 5 15 25 5 15 25 5 15 25 ns ? n = clock frequency synthesis factor
electrical specifications 78 april 2004 ? revised january 2008 sprs245j c1 c3 c2 c12 c4 c9 c8 c6 c7 x2/clkin clkout bypass mode c3 c10 c11 note a: the relationship of x2/clkin to clkout depends on the pll multiply and divide factor chosen for the clkmd register. the waveform relationship shown in figure 5?3 is intended to illustrate the timing parameters based on clkout = 1xclkin configuration. figure 5?4. external multiply-by-n clock timings 5.6.5 real-time clock oscillator with external crystal the real-time clock module includes an oscillator circuit. the oscillator requires an external 32.768-khz crystal connected across the rtcinx1 and rtcinx2 pins. the connection of the required circuit, consisting of the crystal and two load capacitors, is shown in figure 5?5. the load capacitors, c 1 and c 2 , should be chosen such that the equation below is satisfied. c l in the equation is the load specified for the crystal. c l c 1 c 2 ( c 1 c 2 ) rtcinx1 rtcinx2 c1 c2 32.768 khz crystal figure 5?5. real-time clock oscillator with external crystal note: the rtc can be idled by not supplying its 32-khz oscillator signal. in order to keep rtc power dissipation to a minimum when the rtc module is not used, it is recommended that the rtc module be powered up, the rtc input pin (rtcinx1) be pulled low, and the rtc output pin (rtcinx2) be left floating. table 5?6. recommended rtc crystal parameters parameter min nom max unit f o frequency of oscillation ? 32.768 khz esr series resistance ? 30 60 k ? c l load capacitance 12.5 pf dl crystal drive level 1 w ? esr must be 200 k ? or greater at frequencies other than 32.768khz. otherwise, oscillations at overtone frequencies may occur.
electrical specifications 79 april 2004 ? revised january 2008 sprs245j 5.7 memory interface timings 5.7.1 asynchronous memory timings table 5?7 and table 5?8 assume testing over recommended operating conditions (see figure 5?6 and figure 5?7). table 5?7. asynchronous memory cycle timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit m1 t su(dv-coh) setup time, read data valid before clkout high ? 6 5 ns m2 t h(coh-dv) hold time, read data valid after clkout high 0 0 ns m3 t su(ardy-coh) setup time, ardy valid before clkout high ? 10 7 ns m4 t h(coh-ardy) hold time, ardy valid after clkout high 0 0 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. if ardy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, ardy can be an asynchronous input. table 5?8. asynchronous memory cycle switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit m5 t d(coh-cev) delay time, clkout high to cex valid ?2 4 ?2 4 ns m6 t d(coh-ceiv) delay time, clkout high to cex invalid ?2 4 ?2 4 ns m7 t d(coh-bev) delay time, clkout high to bex valid 4 4 ns m8 t d(coh-beiv) delay time, clkout high to bex invalid ?2 ?2 ns m9 t d(coh-av) delay time, clkout high to address valid 4 4 ns m10 t d(coh-aiv) delay time, clkout high to address invalid ?2 ?2 ns m11 t d(coh-aoev) delay time, clkout high to aoe valid ?2 4 ?2 4 ns m12 t d(coh-aoeiv) delay time, clkout high to aoe invalid ?2 4 ?2 4 ns m13 t d(coh-arev) delay time, clkout high to are valid ?2 4 ?2 4 ns m14 t d(coh-areiv) delay time, clkout high to are invalid ?2 4 ?2 4 ns m15 t d(coh-dv) delay time, clkout high to data valid 4 4 ns m16 t d(coh-div) delay time, clkout high to data invalid ?2 ?2 ns m17 t d(coh-awev) delay time, clkout high to awe valid ?2 4 ?2 4 ns m18 t d(coh-aweiv) delay time, clkout high to awe invalid ?2 4 ?2 4 ns
electrical specifications 80 april 2004 ? revised january 2008 sprs245j setup = 2 strobe = 5 not ready = 2 hold = 1 extended hold = 2 clkout ? cex ? bex a[20:0] d[15:0] aoe are awe ardy m5 m7 m6 m8 m9 m10 m1 m2 m12 m14 m11 m13 m3 m4 m3 m4 ? clkout is equal to cpu clock ? cex becomes active depending on the memory address space being accessed a[13:0] for lqfp figure 5?6. asynchronous memory read timings
electrical specifications 81 april 2004 ? revised january 2008 sprs245j setup = 2 strobe = 5 not ready = 2 hold = 1 extended hold = 2 m17 c lkout ? cex ? bex a[20:0] d[15:0] aoe are awe ardy m3 m4 m7 m6 m8 m9 m10 m18 m3 m4 m15 m16 m5 ? clkout is equal to cpu clock ? cex becomes active depending on the memory address space being accessed a[13:0] for lqfp figure 5?7. asynchronous memory write timings
electrical specifications 82 april 2004 ? revised january 2008 sprs245j 5.7.2 synchronous dram (sdram) timings table 5?9 and table 5?10 assume testing over recommended operating conditions (see figure 5?8 through figure 5?14). table 5?9. synchronous dram cycle timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit m19 t su(dv-clkmemh) setup time, read data valid before clkmem high 3 3 ns m20 t h(clkmemh-dv) hold time, read data valid after clkmem high 2 2 ns m21 t c(clkmem) cycle time, clkmem 9.26 ? 7.52 ? ns ? maximum sdram operating frequency = 108 mhz. actual attainable maximum operating frequency will depend on the quality of the pc board design and the memory chip timing requirement. ? maximum sdram operating frequency = 133 mhz. actual attainable maximum operating frequency will depend on the quality of the pc board design and the memory chip timing requirement. table 5?10. synchronous dram cycle switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit m22 t d(clkmemh-cel) delay time, clkmem high to cex low 1.2 7 1.2 5 ns m23 t d(clkmemh-ceh) delay time, clkmem high to cex high 1.2 7 1.2 5 ns m24 t d(clkmemh-bev) delay time, clkmem high to bex valid 1.2 7 1.2 5 ns m25 t d(clkmemh-beiv) delay time, clkmem high to bex invalid 1.2 7 1.2 5 ns m26 t d(clkmemh-av) delay time, clkmem high to address valid 1.2 7 1.2 5 ns m27 t d(clkmemh-aiv) delay time, clkmem high to address invalid 1.2 7 1.2 5 ns m28 t d(clkmemh-sdcasl) delay time, clkmem high to sdcas low 1.2 7 1.2 5 ns m29 t d(clkmemh-sdcash) delay time, clkmem high to sdcas high 1.2 7 1.2 5 ns m30 t d(clkmemh-dv) delay time, clkmem high to data valid 1.2 7 1.2 5 ns m31 t d(clkmemh-div) delay time, clkmem high to data invalid 1.2 7 1.2 5 ns m32 t d(clkmemh-sdwel) delay time, clkmem high to sdwe low 1.2 7 1.2 5 ns m33 t d(clkmemh-sdweh) delay time, clkmem high to sdwe high 1.2 7 1.2 5 ns m34 t d(clkmemh-sda10v) delay time, clkmem high to sda10 valid 1.2 7 1.2 5 ns m35 t d(clkmemh-sda10iv) delay time, clkmem high to sda10 invalid 1.2 7 1.2 5 ns m36 t d(clkmemh-sdrasl) delay time, clkmem high to sdras low 1.2 7 1.2 5 ns m37 t d(clkmemh-sdrash) delay time, clkmem high to sdras high 1.2 7 1.2 5 ns m38 t d(clkmemh?ckel) delay time, clkmem high to cke low 1.2 7 1.2 5 ns m39 t d(clkmemh?ckeh) delay time, clkmem high to cke high 1.2 7 1.2 5 ns
electrical specifications 83 april 2004 ? revised january 2008 sprs245j m22 m24 m26 m27 m23 m34 m28 m35 m29 m19 m20 d1 d2 d3 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe read read read ca1 ca2 ca3 m21 ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals r emain active until the next access that is not an sdram read occurs. figure 5?8. three sdram read commands
electrical specifications 84 april 2004 ? revised january 2008 sprs245j write write write m22 m24 m26 m30 m34 m28 m32 m25 m27 m31 m23 m35 m29 m33 be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals r emain active until the next access that is not an sdram read occurs. figure 5?9. three sdram wrt commands
electrical specifications 85 april 2004 ? revised january 2008 sprs245j m23 m37 m22 m26 m34 m36 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe actv bank activate/row address ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals r emain active until the next access that is not an sdram read occurs. figure 5?10. sdram actv command
electrical specifications 86 april 2004 ? revised january 2008 sprs245j m23 m37 m22 m36 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe m34 m35 m32 m33 dcab ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals r emain active until the next access that is not an sdram read occurs. figure 5?11. sdram dcab command
electrical specifications 87 april 2004 ? revised january 2008 sprs245j m23 m37 m22 m36 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe m28 m29 refr ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals remain active until the next access that is not an sdram read occurs. figure 5?12. sdram refr command
electrical specifications 88 april 2004 ? revised january 2008 sprs245j m23 m37 m22 m36 clkmem cex ? bex ? emif.a[13:0] d[15:0] sda10 sdras sdcas sdwe m32 m33 mrs mrs value 0x30 m26 m27 m28 m29 ? the chip enable that becomes active depends on the address being accessed. ? all be[1:0] signals are driven low (active) during reads. byte manipulation of the read data is performed inside the emif. these signals r emain active until the next access that is not an sdram read occurs. write burst length = 1 read latency = 3 burst type = 0 (serial) burst length = 1 figure 5?13. sdram mrs command
electrical specifications 89 april 2004 ? revised january 2008 sprs245j enter self-refresh m38 m39 m22 m23 m36 m28 clkmem cke (xf or gpio4) cex sdras sdcas sdwe sda10 exit self-refresh figure 5?14. sdram self-refresh command
electrical specifications 90 april 2004 ? revised january 2008 sprs245j 5.8 reset timings 5.8.1 power-up reset (on-chip oscillator active) table 5?11 assumes testing over recommended operating conditions (see figure 5?15). table 5?11. power-up reset (on-chip oscillator active) timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit r1 t h(supstbl-rstl) hold time, reset low after oscillator stable ? 3p ? 3p ? ns ? oscillator stable time depends on the crystal characteristic (i.e., frequency, esr, etc.) which varies from one crystal manufac turer to another. based on the crystal characteristics, the oscillator stable time can be in the range of a few to 10s of ms. a reset circuit with 100 ms or more delay time will ensure the oscillator stabilized before the reset goes high. ? p = 1/(input clock frequency) in ns. for example, when input clock is 12 mhz, p = 83.33 ns. r1 clkout cv dd dv dd reset figure 5?15. power-up reset (on-chip oscillator active) timings
electrical specifications 91 april 2004 ? revised january 2008 sprs245j 5.8.2 power-up reset (on-chip oscillator inactive) table 5?12 and table 5?13 assume testing over recommended operating conditions (see figure 5?16). table 5?12. power-up reset (on-chip oscillator inactive) timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit r2 t h(clkoutv-rstl) hold time, clkout valid to reset low 3p ? 3p ? ns ? p = 1/(input clock frequency) in ns. for example, when input clock is 12 mhz, p = 83.33 ns. table 5?13. power-up reset (on-chip oscillator inactive) switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit r3 t d(clkinv-clkoutv) delay time, clkin valid to clkout valid 30 30 ns cv dd dv dd r3 r2 clkout x2/clkin reset figure 5?16. power-up reset (on-chip oscillator inactive) timings
electrical specifications 92 april 2004 ? revised january 2008 sprs245j 5.8.3 warm reset table 5?14 and table 5?15 assume testing over recommended operating conditions (see figure 5?17). table 5?14. reset timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit r4 t w(rsl) pulse width, reset low 3p ? 3p ? ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. table 5?15. reset switching characteristics ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit r5 t d(rsth-bkv) delay time, reset high to bk group valid ? 38p + 15 38p + 15 ns r6 t d(rsth-highv) delay time, reset high to high group valid 38p + 15 38p + 15 ns r7 t d(rstl-ziv) delay time, reset low to z group invalid ? 1p + 15 1p + 15 ns r8 t d(rsth-zv) delay time, reset high to z group valid ? 38p + 15 38p + 15 ns ? p = 1/cpu clock frequency in ns. for example, when cpu is running at 200 mhz, p = 5 ns. ? bk group: pins with bus keepers, holds previous state during reset. following low-to-high transition of reset , these pins go to their post-reset logic state. bk group pins: a?[0], a[15:0], d[15:0], c[14:2], c0, gpio5, dx1, and dx2 high group: following low-to-high transition of reset , these pins go to logic-high state. high group pins: c1[hpi.hint ], xf ? z group: bidirectional pins which become input or output pins. following low-to-high transition of reset , these pins go to high-impedance state. z group pins: c1[emif.aoe], gpio[7:6, 4:0], tin/tout0, sda, scl, clkr0, fsr0, clkx0, dx0, fsx0, fsx2, clkx2, fsr2, dr2, clkr2, fsx1, clkx1, fsr1, dr1, clkr1, a[20:16] reset bk group ? h igh group ? z group r5 r7 r6 r8 ? bk group pins: a?[0], a[15:0], d[15:0], c[14:2], c0, gpio5, dx1, and dx2 ? high group pins: c1[hpi.hint ], xf z group pins: c1[emif.aoe], gpio[7:6, 4:0], tin/tout0, sda, scl, clkr0, fsr0, clkx0, dx0, fsx0, fsx2, clkx2, fsr2, dr2, clkr2 , fsx1, clkx1, fsr1, dr1, clkr1, a[20:16] figure 5?17. reset timings
electrical specifications 93 april 2004 ? revised january 2008 sprs245j 5.9 external interrupt timings table 5?16 assumes testing over recommended operating conditions (see figure 5?18). table 5?16. external interrupt timing requirements ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit i1 t w(inth)a pulse width, interrupt high, cpu active 2p 2p ns i2 t w(intl)a pulse width, interrupt low, cpu active 3p 3p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. i1 i2 intn figure 5?18. external interrupt timings 5.10 wake-up from idle table 5?17 assumes testing over recommended operating conditions (see figure 5?19). table 5?17. wake-up from idle switching characteristics ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min typ max min typ max unit id1 t d(wkpevtl-clkgen) delay time, wake-up event low to clock generation enable (cpu and clock domain idle) 1.25 ? 1.25 ? ms id2 t h(clkgen-wkpevtl) hold time, clock generation enable to wake-up event low (cpu and clock domain in idle) 3p 3p ns id3 t w(wkpevtl) pulse width, wake-up event low (for cpu idle only) 3p 3p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? estimated data based on 12-mhz crystal used with on-chip oscillator at 25 c. this number will vary based on the actual crystal characteristics operating condition and the pc board layout and the parasitics. following the clock generation domain idle, the intx becomes level-sensitive and stays that way until the low-to-high transition of intx following the cpu wake-up. holding the intx low longer than minimum requirement will send more than one interrupt to the cpu. the number of interrupts sent to the cpu depends on the intx -low time following the cpu wake-up from idle. id1 id2 id3 x1 reset , intx figure 5?19. wake-up from idle timings
electrical specifications 94 april 2004 ? revised january 2008 sprs245j 5.11 xf timings table 5?18 assumes testing over recommended operating conditions (see figure 5?20). table 5?18. xf switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit x1 t d(xf) delay time, clkout high to xf high ?1 3 ?1 3 ns x1 t d(xf) delay time, clkout high to xf low ?1 3 ?1 3 ns x1 clkout ? xf ? clkout reflects the cpu clock. figure 5?20. xf timings
electrical specifications 95 april 2004 ? revised january 2008 sprs245j 5.12 general-purpose input/output (gpio x ) timings table 5?19 and table 5?20 assume testing over recommended operating conditions (see figure 5?21). table 5?19. gpio pins configured as inputs timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit setup time, iox input valid before clkout gpio 4 4 g1 t su(gpio-coh) setup time, iox input valid before clkout high agpio ? 8 8 ns g1 t su(gpio-coh) high ehpigpio ? 8 8 ns hold time, iox input valid after clkout gpio 0 0 g2 t h(coh-gpio) hold time, iox input valid after clkout high agpio ? 0 0 ns h(coh-gpio) high ehpigpio ? 0 0 ? agpio pins: a[15:0] ? ehpigpio pins: c13, c10, c7, c5, c4, and c0 table 5?20. gpio pins configured as outputs switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit delay time, clkout high to iox output gpio 0 6 0 6 g3 t d(coh-gpio) delay time, clkout high to iox outpu t change agpio ? 0 11 0 11 ns d(coh-gpio) change ehpigpio ? 0 13 0 13 ? agpio pins: a[15:0] ? ehpigpio pins: c13, c10, c7, c5, c4, and c0 g3 g1 g2 clkout ? iox input mode iox output mode ? clkout reflects the cpu clock. figure 5?21. general-purpose input/output (iox) signal timings
electrical specifications 96 april 2004 ? revised january 2008 sprs245j 5.13 tin/tout timings (timer0 only) table 5?21 and table 5?22 assume testing over recommended operating conditions (see figure 5?22 and figure 5?23). table 5?21. tin/tout pins configured as inputs timing requirements ?? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit t4 t w(tin/toutl) pulse width, tin/tout low 2p + 1 2p + 1 ns t5 t w(tin/touth) pulse width, tin/tout high 2p + 1 2p + 1 ns ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. ? only the timer0 signal is externally available. the timer1 signal is internally terminated and is not available for external us e. table 5?22. tin/tout pins configured as outputs switching characteristics ?? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit t1 t d(coh-tin/touth) delay time, clkout high to tin/tout high ?1 3 ?1 3 ns t2 t d(coh-tin/toutl) delay time, clkout high to tin/tout low ?1 3 ?1 3 ns t3 t w(tin/tout) pulse duration, tin/tout (output) p ? 1 p ? 1 ns ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. ? only the timer0 signal is externally available. the timer1 signal is internally terminated and is not available for external us e. for proper operation of the tin/tout pin configured as an output, the timer period must be configured for at least 4 cycles. tin/tout as input t5 t4 figure 5?22. tin/tout timings when configured as inputs tin/tout as output clkout t2 t1 t3 figure 5?23. tin/tout timings when configured as outputs
electrical specifications 97 april 2004 ? revised january 2008 sprs245j 5.14 multichannel buffered serial port (mcbsp) timings 5.14.1 mcbsp0 timings table 5?23 and table 5?24 assume testing over recommended operating conditions (see figure 5?24 and figure 5?25). table 5?23. mcbsp0 timing requirements ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit mc1 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ? 2p ? ns mc2 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p?1 ? p?1 ? ns mc3 t r(ckrx) rise time, clkr/x clkr/x ext 6 6 ns mc4 t f(ckrx) fall time, clkr/x clkr/x ext 6 6 ns mc5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 10 7 ns mc5 t su(frh-ckrl ) setup time, external fsr high before clkr low clkr ext 2 2 ns mc6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int ?3 ?3 ns mc6 t h(ckrl-frh ) hold time, external fsr high after clkr low clkr ext 1 1 ns mc7 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 10 7 ns mc7 t su(drv-ckrl ) setup time, dr valid before clkr low clkr ext 2 2 ns mc8 t h(ckrl-drv) hold time, dr valid after clkr low clkr int ?2 ?2 ns mc8 t h(ckrl-drv ) hold time, dr valid after clkr low clkr ext 3 3 ns mc9 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 13 8 ns mc9 t su(fxh-ckxl ) setup time, external fsx high before clkx low clkx ext 3 2 ns mc10 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int ?3 ?3 ns mc10 t h(ckxl-fxh ) hold time, external fsx high after clkx low clkx ext 1 1 ns ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns.
electrical specifications 98 april 2004 ? revised january 2008 sprs245j table 5?24. mcbsp0 switching characteristics ?? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit mc1 t c(ckrx) cycle time, clkr/x clkr/x int 2p 2p ns mc3 t r(ckrx) rise time, clkr/x clkr/x int 1 1 ns mc4 t f(ckrx) fall time, clkr/x clkr/x int 1 1 ns mc11 t w(ckrxh) pulse duration, clkr/x high clkr/x int d?2 d+2 d?1 d+1 ns mc12 t w(ckrxl) pulse duration, clkr/x low clkr/x int c?2 c+2 c?1 c+1 ns mc13 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ?2 1 ?2 1 ns mc13 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr ext 4 13 4 8 ns mc14 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int ?2 2 ?2 2 ns mc14 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 4 15 4 9 ns mc15 t dis(ckxh-dxhz) disable time, dx high-impedance from clkx high clkx int 0 5 ?5 1 ns mc15 t dis(ckxh-dxhz ) disable time, dx high-impedance from clkx high following last data bit clkx ext 10 18 3 11 ns delay time, clkx high to dx valid. clkx int 5 4 delay time, clkx high to dx valid. this applies to all bits except the first bit transmitted . clkx ext 15 9 mc16 t d(ckxh-dxv) delay time, clkx high to dx valid ? dxena = 0 clkx int 4 2 ns mc16 t d(ckxh-dxv ) valid ? dxena = 0 clkx ext 13 7 ns only applies to first bit transmitted when in data delay 1 or 2 dxena = 1 clkx int 2p + 1 2p + 1 when in data delay 1 or 2 (xdatdly = 01b or 10b) modes dxena = 1 clkx ext 2p + 4 2p + 3 enable time, dx driven from clkx high ? dxena = 0 clkx int ?1 ?3 mc17 t en(ckxh-dx) high ? dxena = 0 clkx ext 6 3 ns mc17 t en(ckxh-dx) only applies to first bit transmitted when in data delay 1 or 2 dxena = 1 clkx int p ? 1 p ? 3 ns when in data delay 1 or 2 (xdatdly= 01b or 10b) modes dxena = 1 clkx ext p + 6 p + 3 delay time, fsx high to dx valid ? dxena = 0 fsx int 2 2 mc18 t d(fxh-dxv) only applies to first bit transmitted dxena = 0 fsx ext 13 8 ns mc18 t d(fxh-dxv) only applies to first bit transmitted when in data delay 0 (xdatdly= dxena = 1 fsx int 2p + 1 2p + 1 ns when in data delay 0 (xdatdly= 00b) mode. dxena = 1 fsx ext 2p + 10 2p + 10 enable time, dx driven from fsx high ? dxena = 0 fsx int 0 0 mc19 t en(fxh-dx) high ? dxena = 0 fsx ext 8 3 ns mc19 t en(fxh-dx) only applies to first bit transmitted when in data delay 0 (xdatdly= dxena = 1 fsx int p ? 3 p ? 3 ns when in data delay 0 (xdatdly= 00b) mode dxena = 1 fsx ext p + 8 p + 4 ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t=clkrx period = (1 + clkgdv) * p c=clkrx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * p when clkgdv is even d=clkrx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * p when clkgdv is even ? see the tms320c55x dsp peripherals overview reference guide (literature number spru317) for a description of the dx enable (dxena) and data delay features of the mcbsp.
electrical specifications 99 april 2004 ? revised january 2008 sprs245j 5.14.2 mcbsp1 and mcbsp2 timings table 5?25 and table 5?26 assume testing over recommended operating conditions (see figure 5?24 and figure 5?25). table 5?25. mcbsp1 and mcbsp2 timing requirements ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit mc1 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ? 2p ? ns mc2 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p?1 ? p?1 ? ns mc3 t r(ckrx) rise time, clkr/x clkr/x ext 6 6 ns mc4 t f(ckrx) fall time, clkr/x clkr/x ext 6 6 ns mc5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 11 7 ns mc5 t su(frh-ckrl ) setup time, external fsr high before clkr low clkr ext 3 3 ns mc6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int ?3 ?3 ns mc6 t h(ckrl-frh ) hold time, external fsr high after clkr low clkr ext 1 1 ns mc7 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 11 7 ns mc7 t su(drv-ckrl ) setup time, dr valid before clkr low clkr ext 3 3 ns mc8 t h(ckrl-drv) hold time, dr valid after clkr low clkr int ?2 ?2 ns mc8 t h(ckrl-drv ) hold time, dr valid after clkr low clkr ext 3 3 ns mc9 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 14 9 ns mc9 t su(fxh-ckxl ) setup time, external fsx high before clkx low clkx ext 4 3 ns mc10 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int ?3 ?3 ns mc10 t h(ckxl-fxh ) hold time, external fsx high after clkx low clkx ext 1 1 ns ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns.
electrical specifications 100 april 2004 ? revised january 2008 sprs245j table 5?26. mcbsp1 and mcbsp2 switching characteristics ?? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit mc1 t c(ckrx) cycle time, clkr/x clkr/x int 2p 2p ns mc3 t r(ckrx) rise time, clkr/x clkr/x int 2 2 ns mc4 t f(ckrx) fall time, clkr/x clkr/x int 2 2 ns mc11 t w(ckrxh) pulse duration, clkr/x high clkr/x int d ? 2 d + 2 d ? 2 d + 2 ns mc12 t w(ckrxl) pulse duration, clkr/x low clkr/x int c ? 2 c + 2 c ? 2 c + 2 ns mc13 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ?3 2 ?3 2 ns mc13 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr ext 3 14 3 9 ns mc14 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int ?3 2 ?3 2 ns mc14 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 4 15 4 9 ns mc15 t dis(ckxh-dxhz) disable time, dx high-impedance from clkx high clkx int ?3 3 ?5 1 ns mc15 t dis(ckxh-dxhz ) disable time, dx high-impedance from clkx high following last data bit clkx ext 10 19 3 12 ns delay time, clkx high to dx valid. clkx int 5 3 delay time, clkx high to dx valid. this applies to all bits except the first bit transmitted . clkx ext 15 9 mc16 t d(ckxh-dxv) delay time, clkx high to dx valid ? dxena = 0 clkx int 4 2 ns mc16 t d(ckxh-dxv ) only applies to first bit transmitted dxena = 0 clkx ext 15 9 ns only applies to first bit transmitted when in data delay 1 or 2 dxena = 1 clkx int 2p + 1 2p + 1 when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx ext 2p + 5 2p + 3 enable time, dx driven from clkx high ? dxena = 0 clkx int ?2 ?4 mc17 t en(ckxh-dx) high ? dxena = 0 clkx ext 9 4 ns mc17 t en(ckxh-dx) only applies to first bit transmitted when in data delay 1 or 2 dxena = 1 clkx int p ? 2 p ? 4 ns when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx ext p + 9 p + 4 delay time, fsx high to dx valid ? dxena = 0 fsx int 3 2 mc18 t d(fxh-dxv) only applies to first bit transmitted dxena = 0 fsx ext 13 8 ns mc18 t d(fxh-dxv) only applies to first bit transmitted when in data delay 0 dxena = 1 fsx int 2p + 1 2p + 1 ns when in data delay 0 (xdatdly=00b) mode. dxena = 1 fsx ext 2p + 12 2p + 7 enable time, dx driven from fsx high ? dxena = 0 fsx int 1 0 mc19 t en(fxh-dx) high ? dxena = 0 fsx ext 8 4 ns mc19 t en(fxh-dx) only applies to first bit transmitted when in data delay 0 dxena = 1 fsx int p ? 1 p ? 3 ns when in data delay 0 (xdatdly=00b) mode dxena = 1 fsx ext p + 8 p + 5 ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t = clkrx period = (1 + clkgdv) * p c = clkrx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * p when clkgdv is even d = clkrx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * p when clkgdv is even ? see the tms320c55x dsp peripherals overview reference guide (literature number spru317) for a description of the dx enable (dxena) and data delay features of the mcbsp.
electrical specifications 101 april 2004 ? revised january 2008 sprs245j mc2, mc12 mc2, mc11 mc1 mc3 mc4 mc13 mc13 mc5 mc6 mc7 mc8 bit (n?1) (n?2) (n?3) (n?4) bit (n?1) (n?2) (n?3) bit (n?1) (n?2) mc7 mc8 mc7 mc8 clkr fsr (int) fsr (ext) dr (rdatdly=00b) dr (rdatdly=01b) dr (rdatdly=10b) figure 5?24. mcbsp receive timings mc2, mc12 mc2, mc11 mc1 mc3 mc4 mc14 mc14 mc9 mc10 mc19 mc18 mc16 mc16 mc16 mc17 mc15 mc17 bit 0 bit (n?1) (n?2) (n?3) (n?4) bit 0 bit 0 bit (n?1) (n?2) (n?3) bit (n?1) (n?2) clkx fsx (int) fsx (ext) dx (xdatdly=00b) dx (xdatdly=01b) dx (xdatdly=10b) figure 5?25. mcbsp transmit timings
electrical specifications 102 april 2004 ? revised january 2008 sprs245j 5.14.3 mcbsp as spi master or slave timings table 5?27 to table 5?34 assume testing over recommended operating conditions (see figure 5?26 through figure 5?29). table 5?27. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0) ? ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. master slave master slave unit min max min max min max min max mc23 t su(drv-ckxl) setup time, dr valid before clkx low 15 3 ? 6p 10 3 ? 6p ns mc24 t h(ckxl-drv) hold time, dr valid after clkx low 0 3 + 6p 0 3 + 6p ns mc25 t su(fxl-ckxh) setup time, fsx low before clkx high 5 5 ns mc26 t c(ckx) cycle time, clkx 2p 16p 2p 16p ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. table 5?28. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 0) ? ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter master slave master slave unit min max min max min max min max mc27 t d(ckxl-fxl) delay time, clkx low to fsx low ? t ? 5 t + 5 t ? 4 t + 4 ns mc28 t d(fxl-ckxh) delay time, fsx low to clkx high # c ? 5 c + 5 c ? 4 c + 4 ns mc29 t d(ckxh-dxv) delay time, clkx high to dx valid ?4 6 3p + 3 5p + 15 ?3 3 3p + 3 5p + 8 ns mc30 t dis(ckxl-dxhz) disable time, dx high- impedance following last data bit from clkx low c ? 4 c + 4 c ? 3 c + 1 ns mc31 t dis(fxh-dxhz) disable time, dx high- impedance following last data bit from fsx high 3p+ 4 3p + 19 3p+ 3 3p + 11 ns mc32 t d(fxl-dxv) delay time, fsx low to dx valid 3p + 4 3p + 18 3p + 4 3p + 10 ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t = clkx period = (1 + clkgdv) * 2p c = clkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2p when clkgdv is even ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
electrical specifications 103 april 2004 ? revised january 2008 sprs245j lsb mc25 mc27 mc28 mc26 mc31 mc30 mc29 mc23 mc24 msb clkx fsx dx dr bit (n?1) (n?2) (n?3) (n?4) bit 0 bit 0 bit (n?1) (n?2) (n?3) (n?4) mc32 figure 5?26. mcbsp timings as spi master or slave: clkstp = 10b, clkxp = 0
electrical specifications 104 april 2004 ? revised january 2008 sprs245j table 5?29. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0) ? ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. master slave master slave unit min max min max min max min max mc33 t su(drv-ckxh) setup time, dr valid before clkx high 15 3 ? 6p 10 3 ? 6p ns mc34 t h(ckxh-drv) hold time, dr valid after clkx high 0 3 + 6p 0 3 + 6p ns mc25 t su(fxl-ckxh) setup time, fsx low before clkx high 5 5 ns mc26 t c(ckx) cycle time, clkx 2p 16p 2p 16p ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. table 5?30. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 0) ? ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter master slave master slave unit min max min max min max min max mc27 t d(ckxl-fxl) delay time, clkx low to fsx low ? c ? 5 c + 5 c ? 4 c + 4 ns mc28 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 5 t + 5 t ? 4 t + 4 ns mc35 t d(ckxl-dxv) delay time, clkx low to dx valid ?4 6 3p + 3 5p + 15 ?3 3 3p + 3 5p + 8 ns mc30 t dis(ckxl-dxhz) disable time, dx high- impedance following last data bit from clkx low ?4 4 3p + 4 3p + 19 ?3 1 3p + 3 3p + 12 ns mc32 t d(fxl-dxv) delay time, fsx low to dx valid d ? 4 d + 4 3p + 4 3p + 18 d ? 3 d + 3 3p + 4 3p + 10 ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t = clkx period = (1 + clkgdv) * p c = clkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * p when clkgdv is even d = clkx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * p when clkgdv is even ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
electrical specifications 105 april 2004 ? revised january 2008 sprs245j lsb mc25 mc28 mc26 mc35 mc33 mc34 msb clkx fsx dx dr bit (n?1) (n?2) (n?3) (n?4) bit 0 bit 0 bit (n?1) (n?2) (n?3) (n?4) mc27 mc30 mc32 figure 5?27. mcbsp timings as spi master or slave: clkstp = 11b, clkxp = 0
electrical specifications 106 april 2004 ? revised january 2008 sprs245j table 5?31. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1) ? ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. master slave master slave unit min max min max min max min max mc33 t su(drv-ckxh) setup time, dr valid before clkx high 15 3 ? 6p 10 3 ? 6p ns mc34 t h(ckxh-drv) hold time, dr valid after clkx high 0 3 + 6p 0 3 + 6p ns mc36 t su(fxl-ckxl) setup time, fsx low before clkx low 5 5 ns mc26 t c(ckx) cycle time, clkx 2p 16p 2p 16p ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. table 5?32. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 1) ? ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter master slave master slave unit min max min max min max min max mc37 t d(ckxh-fxl) delay time, clkx high to fsx low ? t ? 5 t + 5 t ? 4 t + 4 ns mc38 t d(fxl-ckxl) delay time, fsx low to clkx low # d ? 5 d + 5 d ? 4 d + 4 ns mc35 t d(ckxl-dxv) delay time, clkx low to dx valid ?4 6 3p + 3 5p + 15 ?3 3 3p + 3 5p + 8 ns mc39 t dis(ckxh-dxhz) disable time, dx high- impedance following last data bit from clkx high d ? 4 d + 4 d ? 3 d + 1 ns mc31 t dis(fxh-dxhz) disable time, dx high- impedance following last data bit from fsx high 3p + 4 3p +19 3p + 3 3p +11 ns mc32 t d(fxl-dxv) delay time, fsx low to dx valid 3p + 4 3p + 18 3p + 4 3p + 10 ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t = clkx period = (1 + clkgdv) * p c = clkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * p when clkgdv is even d = clkx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * p when clkgdv is even ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
electrical specifications 107 april 2004 ? revised january 2008 sprs245j lsb mc36 mc37 mc38 mc26 mc31 mc39 mc35 mc33 mc34 msb clkx fsx dx dr bit (n?1) (n?2) (n?3) (n?4) bit 0 bit 0 bit (n?1) (n?2) (n?3) (n?4) mc32 figure 5?28. mcbsp timings as spi master or slave: clkstp = 10b, clkxp = 1
electrical specifications 108 april 2004 ? revised january 2008 sprs245j table 5?33. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1) ? ? no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. master slave master slave unit min max min max min max min max mc23 t su(drv-ckxl) setup time, dr valid before clkx low 15 3 ? 6p 10 3 ? 6p ns mc24 t h(ckxl-drv) hold time, dr valid after clkx low 0 3 + 6p 0 3 + 6p ns mc36 t su(fxl-ckxl) setup time, fsx low before clkx low 5 5 ns mc26 t c(ckx) cycle time, clkx 2p 16p 2p 16p ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. table 5?34. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 1) ? ? no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter master slave master slave unit min max min max min max min max mc37 t d(ckxh-fxl) delay time, clkx high to fsx low ? d ? 5 d + 5 d ? 4 d + 4 ns mc38 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 5 t + 5 t ? 4 t + 4 ns mc29 t d(ckxh-dxv) delay time, clkx high to dx valid ?4 6 3p + 3 5p + 15 ?3 3 3p + 3 5p + 8 ns mc39 t dis(ckxh-dxhz) disable time, dx high- impedance following last data bit from clkx high ?4 4 3p + 4 3p + 19 ?3 1 3p + 3 3p + 12 ns mc32 t d(fxl-dxv) delay time, fsx low to dx valid c ? 4 c + 4 3p + 4 3p + 18 c ? 3 c + 3 3p + 4 3p + 10 ns ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. ? p = 1/cpu clock frequency. for example, when running parts at 200 mhz, use p = 5 ns. t = clkx period = (1 + clkgdv) * p c = clkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * p when clkgdv is even d = clkx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * p when clkgdv is even ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
electrical specifications 109 april 2004 ? revised january 2008 sprs245j lsb mc26 mc29 mc23 mc24 msb clkx fsx dx dr bit (n?1) (n?2) (n?3) (n?4) bit 0 bit 0 bit (n?1) (n?2) (n?3) (n?4) mc37 mc39 mc36 mc38 mc32 figure 5?29. mcbsp timings as spi master or slave: clkstp = 11b, clkxp = 1
electrical specifications 110 april 2004 ? revised january 2008 sprs245j 5.14.4 mcbsp general-purpose i/o timings table 5?35 and table 5?36 assume testing over recommended operating conditions (see figure 5?30). table 5?35. mcbsp general-purpose i/o timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit mc20 t su(mgpio-coh) setup time, mgpiox input mode before clkout high ? 7 7 ns mc21 t h(coh-mgpio) hold time, mgpiox input mode after clkout high ? 0 0 ns ? mgpiox refers to clkrx, fsrx, drx, clkxx, or fsxx when configured as a general-purpose input. table 5?36. mcbsp general-purpose i/o switching characteristics no. parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. parameter min max min max unit mc22 t d(coh-mgpio) delay time, clkout high to mgpiox output mode ? 0 7 0 7 ns ? mgpiox refers to clkrx, fsrx, clkxx, fsxx, or dxx when configured as a general-purpose output. clkout ? mgpio ? input mode mgpio output mode mc20 mc21 mc22 ? clkout reflects the cpu clock. ? mgpiox refers to clkrx, fsrx, drx, clkxx, or fsxx when configured as a general-purpose input. mgpiox refers to clkrx, fsrx, clkxx, fsxx, or dxx when configured as a general-purpose output. figure 5?30. mcbsp general-purpose i/o timings
electrical specifications 111 april 2004 ? revised january 2008 sprs245j 5.15 enhanced host-port interface (ehpi) timings table 5?37 and table 5?38 assume testing over recommended operating conditions (see figure 5?31 through figure 5?36). table 5?37. ehpi timing requirements no. cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no. min max min max unit e11 t su(hasl-hdsl) setup time, has low before hds low 4 4 ns e12 t h(hdsl-hasl) hold time, has low after hds low 3 3 ns e13 t su(hcntlv-hdsl) setup time, (hr/w , ha[13:0], hbe[1:0] , hcntl[1:0]) valid before hds low 2 2 ns e14 t h(hdsl-hcntliv) hold time, (hr/w , ha[13:0], hbe[1:0] , hcntl[1:0]) invalid after hds low 4 4 ns e15 t w(hdsl) pulse duration, hds low 4p ? 4p ? ns e16 t w(hdsh) pulse duration, hds high 4p ? 4p ? ns e17 t su(hdv-hdsh) setup time, hd bus write data valid before hds high 3 3 ns e18 t h(hdsh-hdiv) hold time, hd bus write data invalid after hds high 4 4 ns e19 t su(hcntlv-hasl) setup time, (hr/w , hbe[1:0] , hcntl[1:0]) valid before has low 3 3 ns e20 t h(hasl-hcntliv) hold time, (hr/w , hbe[1:0] , hcntl[1:0]) valid after has low 4 4 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. table 5?38. ehpi switching characteristics no . parameter cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v unit no . parameter min max min max unit e1 t en(hdsl-hdd)m enable time, hds low to hd bus enabled (memory access) 6 26 6 19 ns e2 t d(hdsl-hdv)m delay time, hds low to hd bus read data valid (memory access) 14p ?? 14p ?? ns e4 t en(hdsl-hdd)r enable time, hds low to hd enabled (register access) 6 26 6 19 ns e5 t d(hdsl-hdv)r delay time, hds low to hd bus read data valid (register access) 26 19 ns e6 t dis(hdsh-hdiv) disable time, hds high to hd bus read data invalid 6 26 6 19 ns e7 t d(hdsl-hrdyl) delay time, hds low to hrdy low (during reads) 18 15 ns e8 t d(hdv-hrdyh) delay time, hd bus valid to hrdy high (during reads) 2 2 ns e9 t d(hdsh-hrdyl) delay time, hds high to hrdy low (during writes) 18 15 ns e10 t d(hdsh-hrdyh) delay time, hds high to hrdy high (during writes) 14p ?? 14p ?? ns e21 t d(coh-hint) delay time, clkout high to hint high/low 0 11 0 8 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? ehpi latency is dependent on the number of dma channels active, their priorities and their source/destination ports. the latency sho wn assumes no competing cpu or dma activity to the memory resource being accessed by the ehpi.
electrical specifications 112 april 2004 ? revised january 2008 sprs245j e21 clkout ? hint ? clkout reflects the cpu clock. figure 5?31. hint timings hcntl0 hr/w read data valid hrdy ha[13:0] hds hcs hd[15:0] (read) valid e16 e14 e13 e1 e10 e2 valid valid write data hd[15:0] (write) e15 e17 e18 read write e6 e8 e7 e9 e13 e14 e15 hbe[1:0] valid valid notes: a. any non-multiplexed access with hcntl0 low will result in hpic register access. for data read or write, hcntl0 must stay high during the ehpi access. b. the falling edge of hcs must occur concurrent with or before the falling edge of hds . the rising edge of hcs must occur concurrent with or after the rising edge of hds . if hds1 and/or hds2 are tied permanently active and hcs is used as a strobe, the timing requirements shown for hds apply to hcs . hrdy is always driven to the same value as its internal state. figure 5?32. ehpi nonmultiplexed read/write timings
electrical specifications 113 april 2004 ? revised january 2008 sprs245j hr/w read data hrdy hcntl[1:0] has hcs hd[15:0] (read) e11 e13 e1 e2 valid (11) write data hd[15:0] (write) e12 e13 e17 e18 read write hds e15 e16 e15 e12 e11 e20 e19 e14 e20 e19 valid (11) e10 e6 e14 e8 e7 e9 hbe[1:0] valid valid note: the falling edge of hcs must occur concurrent with or before the falling edge of hds . the rising edge of hcs must occur concurrent with or after the rising edge of hds . if hds1 and/or hds2 are tied permanently active and hcs is used as a strobe, the timing requirements shown for hds apply to hcs . hrdy is always driven to the same value as its internal state. figure 5?33. ehpi multiplexed memory (hpid) read/write timings without autoincrement
electrical specifications 114 april 2004 ? revised january 2008 sprs245j hr/w read data n hrdy hds has hcs hd[15:0] (read) h pia contents n + 1 n + 2 e11 e12 e15 e16 e20 e13 e1 e2 e19 e14 e6 e8 e7 read data e1 e2 e6 e8 e7 hcntl[1:0] valid (01) valid (01) hbe[1:0] valid valid notes: a. during autoincrement mode, although the ehpi internally increments the memory address, reads of the hpia register by the hos t will always indicate the base address. b. in autoincrement mode, if hbe[1:0] are used to access the data as 8-bit-wide units, the hpia increments only following each high byte (hbe1 low) access. c. the falling edge of hcs must occur concurrent with or before the falling edge of hds . the rising edge of hcs must occu r concurrent with or after the rising edge of hds . if hds1 and/or hds2 are tied permanently active and hcs is used as a strobe , the timing requirements shown for hds apply to hcs . hrdy is always driven to the same value as its internal state. figure 5?34. ehpi multiplexed memory (hpid) read timings with autoincrement
electrical specifications 115 april 2004 ? revised january 2008 sprs245j hr/w write data write data n hrdy hcntl[1:0] hds has hcs hd[15:0] (write) h pia contents valid (01) valid (01) n + 1 e11 e12 e15 e16 e20 e13 e17 e18 e9 e10 e10 e19 e14 e9 hbe[1:0] valid valid notes: a. during autoincrement mode, although the ehpi internally increments the memory address, reads of the hpia register by the hos t will always indicate the base address. b. the falling edge of hcs must occur concurrent with or before the falling edge of hds . the rising edge of hcs must occu r concurrent with or after the rising edge of hds . if hds1 and/or hds2 are tied permanently active and hcs is used as a strobe , the timing requirements shown for hds apply to hcs . hrdy is always driven to the same value as its internal state. figure 5?35. ehpi multiplexed memory (hpid) write timings with autoincrement
electrical specifications 116 april 2004 ? revised january 2008 sprs245j hr/w read data hrdy hcntl[1:0] has hcs hd[15:0] (read) e11 e13 e4 e5 valid (10 or 00) write data hd[15:0] (write) e12 e13 e17 e18 read write hds e15 e16 e15 e12 e11 e20 e19 e14 e20 e19 valid (10 or 00) e14 e6 hbe[1:0] valid valid notes: a. during autoincrement mode, although the ehpi internally increments the memory address, reads of the hpia register by the host will always indicate the base address. b. the falling edge of hcs must occur concurrent with or before the falling edge of hds . the rising edge of hcs must occur concurrent with or after the rising edge of hds . if hds1 and/or hds2 are tied permanently active and hcs is used as a strobe, the timing requirements shown for hds apply to hcs . hrdy is always driven to the same value as its internal state. figure 5?36. ehpi multiplexed register read/write timings
electrical specifications 117 april 2004 ? revised january 2008 sprs245j 5.16 i 2 c timings table 5?39 and table 5?40 assume testing over recommended operating conditions (see figure 5?37 and figure 5?38). table 5?39. i 2 c signals (sda and scl) timing requirements cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v no. standard mode fast mode standard mode fast mode unit min max min max min max min max ic1 t c(scl) cycle time, scl 10 2.5 10 2.5 s ic2 t su(sclh-sdal) setup time, scl high before sda low for a repeated start condition 4.7 0.6 4.7 0.6 s ic3 t h(scll-sdal) hold time, scl low after sda low for a start and a repeated start condition 4 0.6 4 0.6 s ic4 t w(scll) pulse duration, scl low 4.7 1.3 4.7 1.3 s ic5 t w(sclh) pulse duration, scl high 4 0.6 4 0.6 s ic6 t su(sda-sclh) setup time, sda valid before scl high 250 100 ? 250 100 ? ns ic7 t h(sda-scll) hold time, sda valid after scl low 0 ? 0 ? 0.9 0 ? 0 ? 0.9 s ic8 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 4.7 1.3 s ic9 t r(sda) rise time, sda 1000 20 + 0.1c b ? 300 1000 20 + 0.1c b ? 300 ns ic10 t r(scl) rise time, scl 1000 20 + 0.1c b ? 300 1000 20 + 0.1c b ? 300 ns ic11 t f(sda) fall time, sda 300 20 + 0.1c b ? 300 300 20 + 0.1c b ? 300 ns ic12 t f(scl) fall time, scl 300 20 + 0.1c b ? 300 300 20 + 0.1c b ? 300 ns ic13 t su(sclh-sdah) setup time, scl high be- fore sda high (for stop condition) 4.0 0.6 4.0 0.6 s ic14 t w(sp) pulse duration, spike (must be suppressed) 0 50 0 50 ns ic15 c b ? capacitive load for each bus line 400 400 400 400 pf ? a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda-sclh) 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. ? a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. ? c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. i 2 c bus is a trademark of koninklijke philips electronics n.v.
electrical specifications 118 april 2004 ? revised january 2008 sprs245j ic10 ic8 ic4 ic3 ic7 ic12 ic5 ic6 ic14 ic2 ic3 ic13 stop start repeated start stop sda scl ic1 ic11 ic9 figure 5?37. i 2 c receive timings
electrical specifications 119 april 2004 ? revised january 2008 sprs245j table 5?40. i 2 c signals (sda and scl) switching characteristics cv dd = 1.2 v cv dd = 1.35 v cv dd = 1.6 v no. parameter standard mode fast mode standard mode fast mode unit min max min max min max min max ic16 t c(scl) cycle time, scl 10 2.5 10 2.5 s ic17 t d(sclh-sdal) delay time, scl high to sda low for a repeated start condition 4.7 0.6 4.7 0.6 s ic18 t d(sdal-scll) delay time, sda low to scl low for a start and a repeated start condition 4 0.6 4 0.6 s ic19 t w(scll) pulse duration, scl low 4.7 1.3 4.7 1.3 s ic20 t w(sclh) pulse duration, scl high 4 0.6 4 0.6 s ic21 t d(sda-sclh) delay time, sda valid to scl high 250 100 250 100 ns ic22 t v(scll-sdav) valid time, sda valid after scl low 0 0 0.9 0 0 0.9 s ic23 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 4.7 1.3 s ic24 t r(sda) rise time, sda 1000 20 + 0.1c b ? 300 1000 20 + 0.1c b ? 300 ns ic25 t r(scl) rise time, scl 1000 20 + 0.1c b ? 300 1000 20 + 0.1c b ? 300 ns ic26 t f(sda) fall time, sda 300 20 + 0.1c b ? 300 300 20 + 0.1c b ? 300 ns ic27 t f(scl) fall time, scl 300 20 + 0.1c b ? 300 300 20 + 0.1c b ? 300 ns ic28 t d(sclh-sdah) delay time, scl high to sda high for a stop condition 4 0.6 4 0.6 s ic29 c p capacitance for each i 2 c pin 10 10 10 10 pf ? c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. ic25 ic23 ic19 ic18 ic22 ic27 ic20 ic21 ic17 ic18 ic28 stop start repeated start stop sda scl ic16 ic26 ic24 figure 5?38. i 2 c transmit timings
mechanical data 120 april 2004 ? revised january 2008 sprs245j 6 mechanical data 6.1 package thermal resistance characteristics table 6?1 and table 6?2 provide the estimated thermal resistance characteristics for the tms320vc5503 dsp package types. table 6?1. thermal resistance characteristics (ambient) package r ja ( c/w) board type ? airflow (lfm) 37.1 high-k 0 35.1 high-k 150 33.7 high-k 250 ghh and zhh 32.2 high-k 500 ghh and zhh 70.3 low-k 0 61.6 low-k 150 56.5 low-k 250 49.3 low-k 500 71.2 high-k 0 61.8 high-k 150 58.9 high-k 250 pge 54.8 high-k 500 pge 103.6 low-k 0 84.2 low-k 150 77.8 low-k 250 69.4 low-k 500 ? board types are as defined by jedec. reference jedec standard jesd51-9, test boards for area array surface mount package thermal measurements. table 6?2. thermal resistance characteristics (case) package(s) r jc ( c/w) board type ? ghh and zhh 13.8 2s jedec test card pge 13.8 2s jedec test card ? board types are as defined by jedec. reference jedec standard jesd51-9, test boards for area array surface mount package thermal measurements. 6.2 packaging information the following packaging information reflects the most current released data available for the designated device(s). this data is subject to change without notice and without revision of this document.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tms320vc5503ghh active bga mi crosta r ghh 179 160 tbd snpb level-3-220c-168 hr tms320vc5503pge active lqfp pge 144 60 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr TMS320VC5503ZHH active bga mi crosta r zhh 179 160 green (rohs & no sb/br) snagcu level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 7-apr-2009 addendum-page 1

mechanical data mtqf017a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pge (s-pqfp-g144) plastic quad flatpack 4040147 / c 10/96 0,27 72 0,17 37 73 0,13 nom 0,25 0,75 0,45 0,05 min 36 seating plane gage plane 108 109 144 sq sq 22,20 21,80 1 19,80 17,50 typ 20,20 1,35 1,45 1,60 max m 0,08 0 7 0,08 0,50 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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